Memory Device Control Method for Parasitic Capacitance Reduction
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Solution Overview
Problem
The challenge in developing three-dimensional memory devices is the increased electrical resistance of thinner electrode layers and parasitic capacitances caused by thinner interlayer insulating films, which lead to delays in operating speed and potential memory cell malfunctions.
Innovation Solution
A control method for a memory device that involves supplying specific potentials to electrode layers in a controlled sequence to manage potential decay and reduce parasitic capacitances, ensuring efficient operation by maintaining the potential of word lines and selection gates while preventing induced potential fluctuations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If electrode layers are made thinner to increase the number of stacked electrode layers, then the degree of integration of the memory cell array is improved, but the electrical resistance of the electrode layers increases
Solution Approach 1:
The patent applies parameter changes by carefully controlling the thickness parameters of the electrode layers and interlayer insulating films within specific ranges. By optimizing these dimensional parameters, the patent achieves high integration (more stacked layers) while maintaining acceptable electrical resistance levels through precise parameter management.
2Productivity
If interlayer insulating films are made thinner to increase integration, then the degree of integration is improved, but parasitic capacitances between electrode layers increase
Solution Approach 1:
The patent controls the thickness parameter of interlayer insulating films within specific ranges to balance integration density and parasitic capacitance. By optimizing this dimensional parameter, the patent achieves thin film structures for high integration while maintaining sufficient insulation to limit parasitic capacitance effects.
Solution Approach 2:
The patent employs composite interlayer insulating film structures consisting of multiple material layers with different dielectric properties. This composite approach allows achieving low parasitic capacitance through high-k materials while maintaining physical separation and integration density.
3Productivity
If electrode layers and interlayer insulating films are made thinner to increase integration, then the degree of integration is improved, but operating speed is delayed
Solution Approach 1:
The patent optimizes the thickness parameters of conductive layers and insulating films to achieve a balance between integration density and signal propagation speed. By controlling these dimensional parameters within specific ranges, the patent reduces RC time constants while maintaining high integration.
4Productivity
If electrode layers are made thinner to increase integration, then the degree of integration is improved, but memory cells may malfunction
Solution Approach 1:
The patent carefully controls the thickness parameter of electrode layers within specific ranges to ensure reliable memory cell operation while achieving high integration. By optimizing this parameter, the patent maintains sufficient current carrying capacity and potential difference for reliable cell switching.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances the operating speed and reliability of memory devices by minimizing parasitic capacitances and preventing data from being written to unselected memory cells, thereby maintaining the integrity of memory cell operations.
Implementation Method 1
making the interlayer insulating films thinner disadvantageously increases the parasitic capacitances between the electrode layers
Data Source
AI summary
According to one embodiment, a method of controlling a memory device includes supplying a second potential having a first value to a second electrode and simultaneously, or thereafter, supplying a third potential to a third electrode, and thereafter stopping supply of the third potential such that the potential of the third electrode decays while reducing the potential of the second electrode, and thereafter supplying a first potential to the first electrode.