Memory Device Current Reduction via Segmented Verify
Solution Overview
Problem
Current memory device programming techniques consume high average and peak current during the verify operation, particularly in multi-pass programming, due to the need to verify all data states in each programming pass, which increases resource consumption and can lead to uncorrectable errors.
Innovation Solution
The method involves programming memory cells in two sets with different checkpoint data states in the first pass and verifying all programmed data states in a second pass, reducing the number of data states verified in the first pass by dividing memory cells across physical blocks or planes, thereby reducing current demand.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If all data states are verified in each programming pass, then programming reliability is improved, but current consumption increases
Solution Approach 1:
The patent divides memory cells into two sets and verifies each set at different checkpoint data states during the first programming pass. This segmentation allows the verify operation to focus on only half of the bit lines or planes at any given time, reducing peak and average current consumption while maintaining programming reliability through comprehensive verification across both sets in the second pass.
2Manufacturing precision
If verify operations are performed on all bit lines during programming, then programming accuracy is improved, but device complexity increases
Solution Approach 1:
The patent segments the verify operation into two phases: first pass verification at checkpoint data states for half the memory cells, and second pass verification for all memory cells. This segmentation reduces operational complexity during the first pass while ensuring comprehensive verification accuracy is achieved in the second pass.
Solution Approach 2:
The patent applies partial verification in the first programming pass by verifying only checkpoint data states for half of the memory cells, rather than performing complete verification on all cells. This partial action reduces operational complexity and current consumption, with the understanding that full verification accuracy is achieved in the second pass.
Data Source
AI summary
The memory device includes a plurality of memory cells, which include a first set of memory cells and a second set of memory cells. A controller is in communication with the memory cells. The controller is configured to, in a first programming pass and then a second programming pass, program the memory cells of the first and second sets to respective final threshold voltages associated with a plurality of programmed data states. The controller is further configured to, in the first programming pass, verify the first set of memory cells at a first set of checkpoint data states and verify the second set of memory cells at a second set of checkpoint data states that is different than the first set of checkpoint data states.