Memory Device Structure with Decoders in Separate Device Level
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Solution Overview
Problem
Traditional memory device structures have a large footprint and high manufacturing costs due to the separate processing requirements for memory arrays and peripheral circuits, leading to complex and costly manufacturing processes.
Innovation Solution
The memory device structure incorporates decoders and peripheral circuitry within a device level beneath or above a memory array, forming a cylinder that encloses the memory cells, with inter-level conductive lines connecting the array to the decoders and pads without passing through the memory cells, thereby reducing the device's footprint and simplifying manufacturing.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If decoders and peripheral circuits are disposed adjacent to the memory array in the same level, then the device structure is simple and easy to manufacture, but the device footprint and chip size become large
Solution Approach 1:
The patent moves decoders and peripheral circuits from the same level as the memory array to a different level (above or below), utilizing the third dimension (vertical stacking) to reduce the two-dimensional footprint. The perimeter of the memory array defines a cylinder that extends through multiple levels, allowing decoder components to be positioned within this cylindrical volume at a different z-coordinate, effectively converting a planar layout problem into a volumetric solution.
2Ease of manufacture
If decoders and peripheral circuits are manufactured using the same process as the memory array, then manufacturing is simplified, but different processing requirements necessitate complex interleaving of processes
Solution Approach 1:
The patent segments the device into distinct functional levels: the memory array level and the decoder/peripheral circuit level. This segmentation allows each level to be manufactured using optimized processes appropriate to its specific requirements, without forcing a single process to accommodate all components. The cylindrical structure defined by the array perimeter provides a spatial boundary that facilitates this segmentation while enabling integration across levels.
Data Source
AI summary
A memory device structure and method of fabricating the memory device structure is described. The memory device structure has a memory array disposed in a array level and peripheral circuitry, including decoders and other peripheral circuitry, disposed in a device level. The array of memory cells has a perimeter that defines a cylinder that extends above and beneath the array of memory cells. The decoders and the other peripheral circuitry or at least part of the decoders and the other peripheral circuitry are disposed within the cylinder in the device level. The memory device structure also includes a plurality of pads in a pad level. A first plurality of inter-level conductive lines electrically couples the decoders to the bit lines and word lines in the array of memory cells.