Memory Device Direct Data Transfer via Dedicated Pads

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Solution Overview

Problem

Current storage devices face inefficiencies in data transfer operations, particularly during tasks like garbage collection, where repeated data reading and transfer between memory devices slow down operation speed due to reliance on the memory controller for data movement.

Innovation Solution

The implementation of a memory device with an operation mode determiner, pad control signal generator, pad controller, internal command generator, and operation controller allows direct data transfer between memory devices without passing through the memory controller, enabling faster data movement by determining operation modes and generating appropriate control signals for read and program operations.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If data transfer operations go through the memory controller, then data movement can be controlled and managed, but operation speed decreases due to repeated data reading and transfer

Engineering Contradiction:
Improveoperation speedVSAvoiddata transfer path complexity
Core Design Contradiction:
ProductivityVSDevice complexity

Solution Approach 1:

The patent extracts the data transfer function from the memory controller by enabling direct data movement between memory devices through dedicated pads. This allows data to bypass the memory controller during transfer operations, eliminating the bottleneck of repeated reading and transferring through the controller while maintaining controlled data movement capabilities.

Inventive Principle:
Principle #2Taking out (Extraction)

Solution Approach 2:

The patent introduces intermediary pads as dedicated interfaces for direct data transfer between memory devices. These pads act as mediators that enable data to pass directly from one memory device to another without routing through the memory controller, thus improving speed while maintaining structured data movement control.

Inventive Principle:
Principle #24Intermediary (Mediator)

2Speed

If direct data transfer between memory devices is enabled, then operation speed improves by bypassing the memory controller, but device complexity increases due to additional control components

Engineering Contradiction:
Improvedata transfer speedVSAvoidcontrol signal generation complexity
Core Design Contradiction:
SpeedVSDevice complexity

Solution Approach 1:

The patent implements multi-functional pads that can serve different purposes: normal operation mode pads for standard data transfer through the controller, and memory communication operation mode pads for direct data transfer between memory devices. This universal design enables direct transfer capability without requiring completely separate hardware, thus improving speed while limiting the increase in device complexity.

Inventive Principle:
Principle #6Universality (Multi-functionality)

3Productivity

If memory communication operation mode is activated, then data transfer efficiency improves, but reliability requirements increase due to direct data movement between memory devices

Engineering Contradiction:
Improvedata transfer efficiencyVSAvoiddata transfer reliability
Core Design Contradiction:
ProductivityVSReliability

Solution Approach 1:

The patent incorporates feedback mechanisms through operation mode determiners that monitor the operational state and pad control signal generator that adjusts control signals based on feedback. This ensures that direct data transfer operations maintain reliability by continuously monitoring and adjusting parameters, allowing efficient data transfer while meeting reliability requirements through active feedback control.

Inventive Principle:
Principle #23Feedback

Data Source

PatentUS11386938B2Storage device and operating method of the storage device
Publication Date: 2022.07.12 SK HYNIX INC
  • US11386938B2 patent drawing
  • US11386938B2 patent drawing
  • US11386938B2 patent drawing

AI summary

A memory device includes: memory cells; an operation mode determiner for determining any one of a normal operation mode and a memory communication operation mode of communicating data with another memory device; a pad control signal generator for generating a pad control signal for determining a pad to receive a signal corresponding to a data movement command of the memory controller according to the determined operation mode; a pad controller for receiving the signal through the determined pad according to the pad control signal; an internal command generator for generating an internal operation command corresponding to the data movement command according to the determined operation mode; and an operation controller for performing one of a read operation of reading first target data from the memory cells and a program operation of storing second target data in the memory cells, based on the internal operation command.