Memory Device Dynamic Mapping Reduces Uncorrectable Errors
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Solution Overview
Problem
Different memory controller central processing units (CPUs) have varying capabilities for correcting data errors, leading to uncorrectable errors when using incompatible error correction engines.
Innovation Solution
A semiconductor memory device with a memory cell array, data I/O buffer, I/O gating circuit, and control logic circuit that programs a mapping relationship between sub-array blocks and I/O pads based on CPU type, reducing uncorrectable errors detected by the memory controller's ECC engine.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a fixed mapping relationship between sub-array blocks and I/O pads is used, then the device structure is simple, but uncorrectable errors occur when incompatible with different CPU types
Solution Approach 1:
The patent implements dynamic mapping configuration that can be programmed at runtime based on CPU type detection. The I/O gating circuit receives a mapping control signal from control logic that programs the mapping relationship between sub-array blocks and I/O pads according to the specific CPU type, allowing the system to adapt its configuration dynamically rather than being fixed, thereby resolving the contradiction between reliability and device complexity
Solution Approach 2:
The patent changes the mapping parameters (mapping control signal) based on CPU type identifier information. By detecting the CPU type and adjusting the mapping configuration accordingly, the system optimizes error correction capability for different CPU architectures without requiring multiple fixed hardware designs, thus improving reliability while managing complexity through parameter adjustment
2Adaptability or versatility
If multiple mapping configurations are supported for different CPU types, then error correction capability is improved, but the device structure becomes more complex
Solution Approach 1:
The patent creates a universal I/O gating circuit that can function with multiple CPU types through programmable mapping. The single I/O gating circuit structure is designed to be multi-functional, capable of adapting to different CPU architectures by receiving and executing different mapping control signals, thereby achieving broad CPU type compatibility without requiring separate dedicated circuits for each CPU type
Solution Approach 2:
The system performs self-configuration by automatically detecting CPU type identifier information and programming the appropriate mapping relationship without external intervention. The control logic circuit autonomously generates the mapping control signal based on detected CPU type, enabling the device to adapt itself to different CPU types, thus improving versatility while keeping the control mechanism integrated and relatively simple
Data Source
AI summary
A semiconductor memory device includes a memory cell array, a data input/output (I/O) buffer, an I/O gating circuit and a control logic circuit. The memory cell array includes a plurality of sub array blocks arranged in a first direction and a second direction. The data I/O buffer exchanges user data with a memory controller through I/O pads. The I/O gating circuit is connected to the data I/O buffer through data buses and connected to the memory cell array through data I/O lines, and programs mapping relationship between the sub array blocks and the I/O pads, based on a mapping control signal such that uncorrectable errors that are detected by an error correction code engine in the memory controller are reduced. The control logic circuit generates the mapping control signal based on identifier information indicating a type of a central processing unit of the memory controller.