Memory Device Dynamic Repair Routing and Voltage Adjustment
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Solution Overview
Problem
Memory devices face operational disruptions due to failed bit cells, and existing repair mechanisms, such as backup memory circuits, are inflexible and limit chip layout arrangements.
Innovation Solution
A memory device with an analyzing circuit, control circuit, and registers that redirect data paths around failed bit cells, allowing for flexible layout arrangements and adjusting operating conditions to minimize failures, including voltage and transmission rate adjustments.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If backup memory circuits are used for repair, then reliability is improved, but device complexity increases and layout flexibility is reduced
Solution Approach 1:
The patent introduces an analyzing circuit as an intermediary component that detects failed bit cells and generates repair information. This mediator enables the control circuit to redirect data operations away from failed cells without requiring complex backup memory structures, thus improving reliability while maintaining manageable device complexity.
Solution Approach 2:
The patent segments the memory addressing space into operational and non-operational regions by using repair information to identify failed bit cells. The control circuit divides data write and read operations into separate paths: one for healthy cells and another that bypasses failed cells, allowing independent management of different memory regions and improving overall system reliability.
2Reliability
If backup memory circuits are used for repair, then reliability is improved, but layout flexibility is reduced
Solution Approach 1:
The patent implements dynamic repair routing where the control circuit adapts data paths in real-time based on failure locations detected by the analyzing circuit. Instead of fixed backup memory locations, the system dynamically redirects writes to alternative operational cells and reads from alternative sources, providing layout flexibility while maintaining reliability.
Solution Approach 2:
The patent changes the operational parameters of the memory system by adjusting voltage levels and transmission rates based on detected failures. The control circuit modifies write and read operations parameters to accommodate failed bit cells, allowing the same physical layout to adapt to different failure scenarios without requiring redundant memory structures.
3Reliability
If voltage and transmission rate adjustments are made, then reliability is improved, but use of energy increases
Solution Approach 1:
The patent adjusts operational parameters such as voltage levels and transmission rates specifically for operations involving repaired or marginal bit cells. By dynamically changing these parameters only when needed for reliability improvement rather than maintaining elevated levels continuously, the system achieves better reliability while minimizing unnecessary energy consumption.
Data Source
AI summary
A memory device includes at least one first register, a memory circuit, an analyzing circuit, and a control circuit. The memory circuit includes a plurality of bit cells. The analyzing circuit is configured to perform an analyzing process on the bit cells to generate an analyzing result. If the analyzing result indicates that a first bit cell of the bit cells fails, the control circuit establishes a repair process by controlling data to be written into the at least one first register and controlling the data to be read out from the at least one first register.