Semiconductor Memory Device Dynamic Program Voltage Control

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Solution Overview

Problem

Current semiconductor memory devices face challenges in achieving a balance between long lifespan and high-speed operation, particularly in managing the accumulation of electrons in charge storage films during write and erase sequences, which affects the threshold voltage control and device reliability.

Innovation Solution

The semiconductor memory device employs a strategy where the initial value and increase amount of the program voltage are adjusted based on the write and erase number, implementing different program voltage settings for various ranges of write and erase operations to minimize electron accumulation, thereby extending lifespan and ensuring high-speed performance.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Speed

If high program voltage is applied to achieve high-speed write operations, then write speed is improved, but electron accumulation in charge storage film increases reducing device lifespan

Engineering Contradiction:
Improvewrite speedVSAvoiddevice lifespan
Core Design Contradiction:
SpeedVSReliability

Solution Approach 1:

The program voltage is made dynamic rather than fixed. The control circuit adjusts the program voltage level based on the current write/erase cycle count stored in register 41. As the cycle count increases, the program voltage is reduced to minimize electron accumulation and extend device lifespan, while maintaining sufficient speed for operational requirements

Inventive Principle:
Principle #15Dynamics

Solution Approach 2:

The patent changes the parameter of program voltage based on the write/erase cycle number. By storing the cycle count in register 41 and using it to control the program voltage level, the system adapts the voltage parameter over time to balance speed and reliability requirements

Inventive Principle:
Principle #35Parameter changes

2Reliability

If program voltage is reduced to extend device lifespan, then electron accumulation is minimized, but write operation speed decreases

Engineering Contradiction:
Improvedevice lifespanVSAvoidwrite speed
Core Design Contradiction:
ReliabilityVSSpeed

Solution Approach 1:

The control circuit performs preliminary action by counting write/erase cycles and storing the count in register 41 before executing the next write operation. This pre-calculation allows the system to determine the appropriate program voltage level in advance, ensuring both lifespan extension and adequate write speed are achieved

Inventive Principle:
Principle #10Preliminary action

3Productivity

If write and erase operations are performed repeatedly, then data storage capacity is utilized, but electron accumulation in charge storage film increases affecting threshold voltage control

Engineering Contradiction:
Improvedata storage utilizationVSAvoidthreshold voltage control
Core Design Contradiction:
ProductivityVSManufacturing precision

Solution Approach 1:

The system implements feedback by using the write/erase cycle count stored in register 41 to control the program voltage level. This feedback mechanism allows the system to adapt to the accumulated electron charge in the charge storage film and adjust the program voltage accordingly, maintaining precise threshold voltage control even after repeated write and erase operations

Inventive Principle:
Principle #23Feedback

Data Source

PatentUS11101008B2Semiconductor memory device
Publication Date: 2021.08.24 KIOXIA CORP
  • US11101008B2 patent drawing
  • US11101008B2 patent drawing
  • US11101008B2 patent drawing

AI summary

A semiconductor memory device includes a memory transistor, a word line, a peripheral circuit, and electrodes connected to the peripheral circuit. In response to a write command via the electrodes, the peripheral circuit can execute a first program operation of applying a first program voltage to the word line one time when the write command is one of an n1-th write command to an n2-th write command corresponding to the memory transistor; and execute a second program operation of applying a second program voltage to the first word line at least one time when the write command is one of an (n2+1)-th write command to an n3-th write command corresponding to the memory transistor. The second program voltage in a k-th second program operation is less than the first program voltage in a k-th first program operation.