Memory Device EMI Reduction via Asymmetric Control Signal Routing

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Solution Overview

Problem

Existing USB memory devices face challenges in minimizing electromagnetic interference (EMI) due to higher frequency control signals, which can be exacerbated by longer wire lengths for control signals, especially in high-speed data transfer protocols like USB3.0.

Innovation Solution

A memory device configuration that includes a controller and non-volatile memory with a periodic control signal sent from a terminal on the controller to the non-volatile memory, reducing wire length for control signals and employing symmetric and equalized transmission paths for differential signals to mitigate EMI, while supporting high-speed data rates.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If higher frequency control signals are used for high-speed data transfer, then data rate is improved, but electromagnetic interference increases

Engineering Contradiction:
Improvedata rateVSAvoidelectromagnetic interference
Core Design Contradiction:
ProductivityVSObject-generated harmful factors

Solution Approach 1:

The patent applies asymmetry by implementing different wire length configurations for control signals versus differential data signals. Specifically, control signal wires are minimized in length and routed directly from the USB controller to the NAND memory, while differential signal paths maintain symmetry. This asymmetric approach prioritizes minimizing EMI generation at the control signal level while preserving high-speed data transfer capability.

Inventive Principle:
Principle #4Asymmetry

Solution Approach 2:

The patent segments the signal transmission paths into distinct categories: control signal paths and differential data signal paths. Each segment is optimized independently - control signals use minimized wire lengths with direct routing, while differential signals use balanced symmetric paths. This segmentation allows targeted EMI mitigation for control signals without compromising overall system performance.

Inventive Principle:
Principle #1Segmentation

2Object-generated harmful factors

If wire length for control signals is reduced, then electromagnetic interference is suppressed, but device complexity increases

Engineering Contradiction:
Improveelectromagnetic interferenceVSAvoidwire routing complexity
Core Design Contradiction:
Object-generated harmful factorsVSDevice complexity

Solution Approach 1:

The patent merges the control signal transmission function directly into the existing USB controller-NAND memory interface structure. By integrating control signal routing within the same physical interface used for data transfer, the patent eliminates the need for separate dedicated control signal wires, thereby reducing overall wire length and EMI without adding significant routing complexity.

Inventive Principle:
Principle #5Merging (Combining)

3Object-generated harmful factors

If symmetric transmission paths are used for differential signals, then electromagnetic interference is reduced, but manufacturing precision requirements increase

Engineering Contradiction:
Improveelectromagnetic interferenceVSAvoidwire length equality
Core Design Contradiction:
Object-generated harmful factorsVSManufacturing precision

Solution Approach 1:

The patent implements partial symmetry by ensuring that differential signal pairs maintain equal wire lengths only where necessary for EMI cancellation, rather than enforcing symmetry across the entire signal path. This partial application of symmetry reduces the manufacturing precision burden while still achieving the critical EMI mitigation benefit in the most sensitive signal transmission segments.

Inventive Principle:
Principle #16Partial or excessive action

Data Source

PatentUS9671818B2Memory device
Publication Date: 2017.06.06 KIOXIA CORP
  • US9671818B2 patent drawing
  • US9671818B2 patent drawing
  • US9671818B2 patent drawing

AI summary

According to one embodiment, a memory controller sends a periodic control signal from a first terminal on a non-volatile memory side to the non-volatile memory, and the control signal includes a data strobe signal, a write enable signal, and a read enable signal.