Semiconductor Memory Device Erase-Write Cycle Control
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Solution Overview
Problem
Semiconductor memory devices face challenges in maintaining reliability due to the degradation of memory cells over erase-write cycles, leading to reduced performance and increased error rates during erase operations.
Innovation Solution
The semiconductor memory device incorporates a method where dummy word lines are controlled using Erase-Write cycling information to apply pre-program voltage pulses and erase voltages, with an erase prohibition voltage applied to dummy cells based on the number of erase-write cycles, thereby optimizing the erase operation and maintaining cell threshold voltages.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If erase operations are performed repeatedly on memory blocks, then data storage capacity is maintained, but memory cell degradation increases leading to reduced reliability
Solution Approach 1:
The patent applies a pre-program voltage pulse to dummy word lines before performing the erase operation on the selected memory block. This preliminary action prepares the dummy cells by programming them in advance, which compensates for the degradation that occurs during subsequent erase-write cycles, thereby maintaining memory cell reliability over extended operational life
Solution Approach 2:
The patent dynamically adjusts the dummy word line voltage based on the erase-write cycle count of the selected memory block. As the number of erase-write cycles increases, the dummy word line voltage is modified to compensate for cell degradation, ensuring that memory cell reliability is maintained throughout the device's operational lifespan
2Manufacturing precision
If dummy cells are fully erased along with normal memory cells, then erase operation simplicity is maintained, but threshold voltage control accuracy deteriorates
Solution Approach 1:
The patent divides the memory block into normal memory cells and dummy cells, applying different voltage control strategies to each segment. During the erase operation, normal memory cells are fully erased while dummy cells receive controlled pre-program voltage pulses, allowing independent threshold voltage management for each cell type and improving overall control precision
Solution Approach 2:
The patent applies different voltage characteristics to different regions of the memory block. Dummy word lines receive pre-program voltage pulses with specific amplitude and duration tailored to their degradation level, while normal word lines receive standard erase voltages. This localized quality control ensures precise threshold voltage management without requiring complete redesign of the erase operation
Data Source
AI summary
Provided herein is a semiconductor memory device and a method for operating the same. The semiconductor memory device may include a memory cell array including a plurality of memory blocks, each including dummy cells coupled to dummy word lines and normal memory cells coupled to normal word lines, a peripheral circuit configured to perform an erase operation on a memory block selected from among the plurality of memory blocks and control logic configured to control the peripheral circuit, during the erase operation, to apply a pre-program voltage pulse to the dummy word lines and the normal word lines, and to control application of dummy word line voltages to the dummy word lines based on Erase-Write (EW) cycling information while applying an erase voltage to a common source line of the selected memory block, wherein the EW cycling information indicates a number of erase-write cycles of the selected memory block.