Semiconductor Memory Device Erase Operation Optimization
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Solution Overview
Problem
Flash memory cells experience data retention issues due to charge loss over time, leading to read errors and reliability concerns, especially as the threshold voltage decreases, necessitating improved erase operations to maintain data integrity.
Innovation Solution
A semiconductor memory device configuration that performs an erase operation by applying inhibition and erase voltages to specific word line groups in intervals, reflecting the structural characteristics of adjacent memory cells to reduce erase distribution width and enhance data retention.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional erase operation is applied to flash memory cells, then the erase operation can be completed, but the erase distribution width increases and data retention characteristics of adjacent memory cells deteriorate
Solution Approach 1:
The memory cell array is divided into multiple blocks (first block and second block), and the erase operation is segmented to be performed on different blocks at different times. During the erase operation of the first block, a read disturbance prevention operation is performed on the second block, thereby preventing erase distribution width expansion and maintaining data retention characteristics of adjacent memory cells.
Solution Approach 2:
Before performing the erase operation on the first block, a read disturbance prevention operation is preliminarily performed on the second block. This preliminary action prepares the adjacent block by applying appropriate voltages to prevent read disturbance during the subsequent erase operation, thereby maintaining data integrity and reducing erase distribution width.
2Reliability
If charge is stored in programmed memory cell, then data is retained, but charge loss over time causes threshold voltage decrease and read errors
Solution Approach 1:
The semiconductor memory device performs verification operations after erase operations to monitor the state of memory cells. By verifying whether the erase operation has been properly completed and detecting any charge loss or threshold voltage shifts, the system can identify and correct issues before they lead to read errors, thereby maintaining data retention reliability over time.
Data Source
AI summary
A semiconductor memory device includes a source layer, a channel structure, gate electrodes on the source layer and spaced apart on a sidewall of the channel structure, and a common source line. The gate electrodes include a first word line group including first and second gate electrodes and a second word line group including third and fourth gate electrodes. The semiconductor memory device, in response to a voltage of the common source line reaching a target voltage, causes an inhibition voltage to be applied to the second word line group and an erase voltage to be applied to the first word line group in a first erase operation interval, and causes the inhibition voltage to be applied to the first word line group and the erase voltage to be applied to the second word line group in a second erase operation interval.