Semiconductor Memory Device Erase Control via Tail Detection
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Solution Overview
Problem
Current semiconductor memory devices face challenges in efficiently erasing data due to inter-cell interference and the need for precise voltage control during erase operations, which affects the reliability and speed of data erasure.
Innovation Solution
The semiconductor memory device employs a method involving upper and lower tail detection and write-back operations, where specific voltage applications and bit line charging strategies are used to verify and adjust the threshold voltages of memory cell transistors, ensuring all cells are properly erased without over-erasing, thereby enhancing reliability and speed.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If a high voltage is applied to the semiconductor layer during erase operation, then the data erasure speed is improved, but the risk of over-erasing and inter-cell interference increases
Solution Approach 1:
The patent applies preliminary action by performing a first erase operation with a high voltage (second voltage) applied to the semiconductor layer to quickly erase most data, followed by a second erase operation with a lower voltage (third voltage) to complete the erasure and prevent over-erasing. This two-stage approach resolves the contradiction by using the high voltage only temporarily for speed, then reducing voltage for reliability in the final stage.
Solution Approach 2:
The patent implements periodic action by dividing the erase operation into multiple discrete steps with different voltage levels. The first erase operation uses a higher voltage for a specific time period, then the second erase operation uses a lower voltage for another time period. This periodic variation in voltage application allows the system to achieve both fast erasure and reliable prevention of over-erasing.
2Reliability
If multiple verify operations are performed to ensure complete erasure, then the reliability is improved, but the total erasure time increases
Solution Approach 1:
The patent performs a first verify operation after the first erase operation to check if erasure is complete before proceeding to the second erase operation. This preliminary verification allows the system to potentially skip the second erase operation if the first was sufficient, thereby reducing total time while maintaining reliability through conditional verification.
Solution Approach 2:
The verify operations provide feedback about the erasure status to control whether additional erase operations are needed. The system uses the verification results to dynamically adjust the erase process, performing only the necessary operations to achieve complete erasure, thus balancing reliability with time efficiency.
3Reliability
If precise voltage control is implemented to prevent over-erasing, then the reliability is improved, but the device complexity increases
Solution Approach 1:
The patent segments the voltage control into distinct levels: a first voltage for normal operation, a second voltage (higher than first) for the first erase operation, and a third voltage (lower than second) for the second erase operation. By dividing the voltage control into discrete segments rather than continuous adjustment, the device achieves precise threshold voltage control while keeping the control mechanism relatively simple.
Solution Approach 2:
The patent changes the voltage parameter between erase operations to control the erasure process. The first erase operation uses a higher voltage (second voltage) for aggressive erasure, then the second erase operation uses a lower voltage (third voltage) for fine-tuned completion. This parameter change approach allows reliable threshold voltage control through simple voltage level switching rather than complex continuous control.
Data Source
AI summary
According to one embodiment, a semiconductor memory device includes: first and second memory cells; a first and second word lines; and a first bit line. The device is configured to execute first to sixth operations. In the first operation, a first voltage is applied to the first word line and a second voltage is applied to a semiconductor layer. In the second operation, the first voltage is applied to the second word line. In the third operation, a third voltage is applied to the first word line. In the fourth operation, the third voltage is applied to the second word line. In the fifth operation, a fourth voltage is applied to the first word line. In the sixth operation, the fourth voltage is applied to the second word line.