Semiconductor Memory Device Erase Operation Trap Formation
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Solution Overview
Problem
Current semiconductor memory devices face inefficiencies in erase operations, particularly in forming traps necessary for effective gate-induced drain leakage (GIDL) current generation, which affects erase speed and voltage requirements.
Innovation Solution
The semiconductor memory device incorporates a control logic to form traps in the channel area below source select transistors by applying specific voltage control signals, including a pre-erase voltage and erase voltage, to enhance the erase operation efficiency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If conventional erase operation is performed without preliminary trap formation, then the erase process is simpler, but the erase speed is slower and higher voltage is required
Solution Approach 1:
The patent applies preliminary action by forming traps in the channel area below source select transistors before the actual erase operation. This is achieved by applying a first source line control voltage and a first setting voltage to generate GIDL current that creates interface traps, which then facilitate faster charge removal during the subsequent erase operation using pre-erase and erase voltages.
2Productivity
If high voltage is applied to form traps before erase, then erase efficiency is improved, but the voltage requirement increases
Solution Approach 1:
The patent employs parameter changes by using multiple voltage stages: a first source line control voltage combined with a first setting voltage to generate GIDL current for trap formation, then transitioning to pre-erase voltage and erase voltage for the actual erasure. This staged parameter change optimizes both efficiency and energy consumption by preparing the channel state before applying high erase voltages.
3Loss of time
If trap formation is performed before erase operation, then the time needed for erasure is reduced, but the total operation time increases due to additional steps
Solution Approach 1:
The patent maintains continuity of useful action by seamlessly integrating trap formation and erase operations through continuous voltage application. The first source line control voltage and first setting voltage are applied to form traps, then pre-erase voltage and erase voltage are applied without interrupting the overall erasure process, ensuring the channel remains in an optimal state throughout the operation.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach improves the efficiency of the erase operation by facilitating GIDL current generation, reducing the time and voltage needed for erasure, thereby enhancing the electrical characteristics of the memory device.
Implementation Method 1
forming an interface trap in a channel area below a source select transistor by applying a first source line control voltage to a source line of a selected memory block among a plurality of memory blocks and applying a first setting voltage to at least one first source select transistor disposed at an outermost position among a plurality of source select transistors of the selected memory block
Data Source
AI summary
Provided herein may be a semiconductor memory device. The semiconductor memory device may include: a memory cell array including a plurality of memory blocks; a peripheral circuit configured to apply an erase voltage to a source line and a plurality of select lines of a selected memory block among the plurality of memory blocks during an erase operation; and a control logic configured to control the peripheral circuit to form a trap in an area below at least one of a plurality of source select transistors included in the selected memory block, before the erase voltage is applied to the selected memory block.