Memory Device Erase Voltage Control
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Solution Overview
Problem
Current memory devices face challenges in efficiently executing erase operations across multiple blocks with varying erase intensities, leading to inefficiencies and potential data integrity issues during simultaneous erase sequences.
Innovation Solution
A memory device configuration that includes a control circuit capable of applying different erase voltages to word lines in separate blocks, allowing for distinct erase intensities during erase operations, ensuring precise control and optimization of erase sequences across multiple blocks.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If a single erase voltage is applied to all blocks during an erase operation, then the device complexity is reduced and ease of operation is improved, but the productivity decreases because all blocks must be erased with the same intensity regardless of their individual needs
Solution Approach 1:
The memory device segments the erase operation by dividing blocks into different erase groups, where each group can receive customized erase voltages. The control circuit assigns blocks to different erase groups based on their erase requirements, allowing simultaneous execution of multiple erase sequences with different intensities, thereby improving overall erase efficiency without requiring complete redesign of the control architecture.
Solution Approach 2:
The patent implements local quality by applying different erase voltages to different blocks based on their specific erase needs. The control circuit determines which blocks require stronger or weaker erase intensities and applies customized voltages accordingly, rather than using a uniform erase voltage for all blocks. This localized approach optimizes erase performance for each block while maintaining system-wide coordination.
2Productivity
If different erase voltages are applied to different blocks simultaneously, then the productivity of erase operations is improved by tailoring erase intensities to specific blocks, but the device complexity increases due to the need for multiple voltage levels and control mechanisms
Solution Approach 1:
The control circuit dynamically adjusts erase voltages applied to different blocks based on real-time requirements. During the erase operation, the control circuit can modify voltage levels for different erase groups as needed, allowing flexible adaptation to varying block conditions. This dynamic control enables optimized erase performance while managing complexity through intelligent voltage allocation rather than fixed voltage schemes.
Solution Approach 2:
The patent employs periodic action by executing multiple erase sequences in an alternating or interleaved manner across different blocks. The control circuit schedules erase operations for different erase groups in a coordinated sequence, applying different voltages at different time periods. This periodic execution pattern allows thorough erasure of all blocks while managing voltage complexity through time-multiplexed control.
3Loss of time
If multiple erase sequences are executed simultaneously with different intensities, then the loss of time is reduced by parallel processing, but the reliability may be compromised due to potential interference between concurrent erase operations
Solution Approach 1:
The memory device segments blocks into different erase groups that can be erased simultaneously with different voltages. By dividing the memory space into independent erase groups, the system can execute multiple erase sequences in parallel without interference between them. This segmentation ensures that concurrent operations do not compromise data integrity while maximizing time efficiency through parallel processing.
Solution Approach 2:
The control circuit acts as an intermediary that coordinates and manages multiple simultaneous erase sequences. It monitors and controls the voltage application to different erase groups, ensuring that concurrent erase operations are properly synchronized and do not interfere with each other. This intermediary control mechanism maintains reliability by preventing cross-talk or interference between parallel erase operations.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables simultaneous and efficient erase operations across multiple blocks, improving data integrity and operational efficiency by tailoring erase intensities to specific blocks, thereby enhancing overall memory system performance.
Implementation Method 1
a control circuit configured to execute an erase sequence for the plurality of blocks, and determine voltages to be applied to a plurality of word lines... applies a first voltage to each of the plurality of word lines to supply a first erase pulse having a first erase intensity to each of the plurality of blocks
Data Source
AI summary
A memory device includes a first block including a first memory cell and a first word line connected to the first memory cell, a second block including a second memory cell and a second word line connected to the second memory cell, and a control circuit. The control circuit applies a first voltage to each of the first and second word lines to supply a first erase pulse having a first erase intensity to each of the first and second blocks, when a first erase operation is executed, and applies the first voltage to the first word line and a second voltage higher than the first voltage to the second word line, to supply the first erase pulse to the first block and a second erase pulse having a second erase intensity less than the first erase intensity to the second block, when a second erase operation is executed.