Semiconductor Memory Device Erase Voltage Control
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Solution Overview
Problem
Semiconductor memory devices with three-dimensional array structures face degradation due to high electric fields during repeated erase operations, leading to memory cell degradation.
Innovation Solution
A semiconductor memory device design that includes a memory cell array with normal pass transistors coupled between global and local word lines, where the address decoder gradually increases the voltage difference between the global and block word lines during erase operations, and applies a ground voltage to the local word lines through the global word lines to prevent electrical overstress.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If a high electric field is produced between channel and word line during erase operation, then erase operation can be performed, but memory cell degradation occurs due to repeated high electric field exposure
Solution Approach 1:
The patent applies dynamics by making the voltage applied to the word line changeable over time. During erase operation, the word line voltage is initially set high to enable effective erasure, then gradually reduced to lower levels. This dynamic voltage adjustment allows the system to achieve both effective erase operation and reduced stress on memory cells during the process, resolving the contradiction between erase capability and cell durability.
2Productivity
If voltage difference between global word line and local word line is large, then erase operation is effective, but electrical overstress occurs leading to memory cell degradation
Solution Approach 1:
The patent applies preliminary action by performing a voltage reduction step before completing the erase operation. After the initial high-voltage erase pulse is applied, the system subsequently reduces the word line voltage to a lower level. This preliminary voltage reduction prevents excessive electrical stress from persisting, thereby protecting memory cells while maintaining erase effectiveness during the critical phase of the operation.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach prevents memory cell degradation by gradually reducing the voltage difference between the global and local word lines, reducing the risk of electrical overstress and extending the device's operational lifespan.
Implementation Method 1
a high electric field may be produced between a channel of a memory cell and a word line
Implementation Method 2
applying a ground voltage to the local word lines through the global word lines
Data Source
AI summary
A semiconductor memory device according to an embodiment of the present invention may include a memory cell array having a plurality of memory cells, a pass transistor group having normal pass transistors coupled between global word lines and local word lines to which the plurality of memory cells are coupled, and an address decoder coupled to the global word lines and a block word line to which gates of the normal pass transistors are coupled in common, wherein the address decoder gradually increases a voltage, obtained by subtracting a voltage of the global word lines from a voltage of the block word line, when an erase voltage is provided to a channel of the plurality of memory cells.