Memory Device Error Interface Segmentation

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Solution Overview

Problem

In memory system architectures, error correction performed before data reaches the memory controller prevents the system from utilizing error information for operational decisions, limiting system management capabilities.

Innovation Solution

A memory device with a controller that transmits data and error information through separate interfaces, allowing error information generated during data correction to be communicated to the processor via an out-of-band path, enabling system management decisions even without processor-based error correction.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Loss of energy

If error correction is performed within the memory device before data is transmitted to the memory controller, then power consumption and cost are reduced, but error information becomes unavailable to the system for operational decisions

Engineering Contradiction:
Improvepower consumptionVSAvoiderror information availability
Core Design Contradiction:
Loss of energyVSLoss of information

Solution Approach 1:

The patent segments the error handling functionality by separating error correction (performed in the memory device) from error information reporting (transmitted separately via error interface). This allows the memory device to correct errors locally while still providing error information to the system through a dedicated error reporting mechanism.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent introduces an intermediary error interface that acts as a mediator between the memory device and the memory controller. This separate interface transmits error information independently from the data path, enabling error information to reach the system even when error correction occurs within the memory device.

Inventive Principle:
Principle #24Intermediary (Mediator)

2Device complexity

If error correction is performed within the memory device, then device complexity is reduced, but the system cannot make operational decisions based on error information

Engineering Contradiction:
Improvememory controller complexityVSAvoidsystem management capability
Core Design Contradiction:
Device complexityVSAdaptability or versatility

Solution Approach 1:

The patent segments error handling into two independent pathways: data transmission through the data interface and error information transmission through the error interface. This segmentation allows the memory controller to remain simpler while the system retains full access to error information for operational decisions.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The error interface serves as an intermediary that bridges the gap between simplified memory device error correction and system-level error management needs. It provides the necessary error information to the system without requiring complex error correction capabilities in the memory controller.

Inventive Principle:
Principle #24Intermediary (Mediator)

3Loss of information

If a separate error interface is added to transmit error information, then error information availability is improved, but device complexity increases

Engineering Contradiction:
Improveerror information availabilityVSAvoidmemory device interface complexity
Core Design Contradiction:
Loss of informationVSDevice complexity

Solution Approach 1:

The error interface is designed as a multi-functional component that handles both error information transmission and can potentially carry other management information. This universal interface approach justifies the added complexity by providing multiple benefits from a single added interface.

Inventive Principle:
Principle #6Universality (Multi-functionality)

Solution Approach 2:

The memory device performs error correction autonomously within itself, serving its own error correction needs without requiring complex error correction capabilities in the memory controller. This self-service approach reduces overall system complexity despite adding an error interface.

Inventive Principle:
Principle #25Self-service

Data Source

PatentUS10002043B2Memory devices and modules
Publication Date: 2018.06.19 SAMSUNG ELECTRONICS CO LTD
  • US10002043B2 patent drawing
  • US10002043B2 patent drawing
  • US10002043B2 patent drawing

AI summary

A memory device includes a memory, a data interface, an error interface and a controller. The data interface communicates data to and from the memory device through an external main memory path. The error interface communicates error information from the memory device through an external system control path and that is separate from the main memory path. The controller is coupled to the data interface, the error interface, and the memory. The controller includes an ECC engine and an ECC controller. The ECC engine corrects an error in data that is read from the memory and generates corrected data by encoding data written to the memory and decoding data read from the memory, generates error information, transmits the corrected data through the data interface, and transmits the error information through the error interface. The ECC controller records the error information in response to the ECC engine.