Semiconductor Memory Device ROM Fuse Area Reduction
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Solution Overview
Problem
In three-dimensionally stacked NAND flash memory devices, the large erase unit area and increased number of source interconnections lead to a significant area penalty due to the presence of dummy bit lines, which reduces storage capacity and increases chip area.
Innovation Solution
The semiconductor memory device effectively utilizes cells in shunt and dummy bit line regions as ROM fuses to store management data, allowing for increased storage capacity by connecting memory strings in parallel with dummy bit lines, thereby reducing the area required for ROM fuses and enhancing cell capacity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If memory strings are connected in parallel with dummy bit lines to ensure reliable operations, then reliability is improved, but chip area increases due to the presence of dummy bit lines and ROM fuse regions
Solution Approach 1:
The patent makes dummy bit lines and cells in shunt regions serve dual purposes: they maintain their original function for reliable memory operations while simultaneously storing management data as ROM fuses. This multi-functionality eliminates the need for separate ROM fuse structures, thereby reducing chip area while maintaining reliability
Solution Approach 2:
The patent merges the ROM fuse function with the dummy bit line structure by forming memory strings connected to dummy bit lines and utilizing them to store management data. This consolidation combines two previously separate functions (reliability enhancement and data storage) into a single integrated structure, reducing overall chip area
2Quantity of substance
If cells in shunt and dummy bit line regions are utilized as ROM fuses to store management data, then storage capacity is improved, but device complexity increases due to additional interconnections and control mechanisms
Solution Approach 1:
The same memory string structures serve multiple functions: regular memory storage and ROM fuse data storage. By making the dummy bit line-connected cells serve as both memory elements and fuse elements, the patent avoids creating separate complex interconnection systems for ROM fuses, thereby increasing storage capacity while limiting complexity growth
Solution Approach 2:
The memory strings connected to dummy bit lines self-serve as ROM fuses without requiring separate control mechanisms. The existing select transistors and interconnection structures are reused to control both regular memory operations and fuse data reading, eliminating the need for additional complex control circuitry
3Productivity
If three-dimensionally stacking memory layers is implemented to increase storage capacity, then productivity is improved, but manufacturing precision requirements increase due to complex batch processing
Solution Approach 1:
The patent divides the chip area into distinct functional regions (first cell array region, second cell array region, shunt region, dummy bit line regions) that can be independently processed and controlled during manufacturing. This segmentation allows for more manageable batch processing with reduced precision requirements compared to uniformly processing the entire stacked structure
Data Source
AI summary
According to one embodiment, a semiconductor memory device comprises a first silicon pillar including a first pair of columnar portions and a first connection portion, a second silicon pillar including a second pair of columnar portions and a second connection portion in the shunt region, the second silicon pillar being adjacent to the first silicon pillar, a first interconnection connected to one of the first pair of columnar portions of the first silicon pillar, a second interconnection connected to one of the second pair of columnar portions of the second silicon pillar. The first interconnection is connected to a dummy bit line. The first interconnection and the second interconnection are connected on the same level.