Semiconductor Memory Device ROM Fuse Error Correction
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Solution Overview
Problem
Three-dimensional NAND flash memory devices face defects such as open and short defects in memory holes, which can lead to incorrect reading of ROM fuse information, essential for operating the memory, and existing technologies lack effective mechanisms for error correction during power-on read.
Innovation Solution
The semiconductor memory device multiplexes ROM fuse information across multiple pages and employs a majority logic operation to correct errors, ensuring reliable data retrieval even in the presence of defects, using a configuration that includes a memory cell array, latch circuits, and an arithmetic operation circuit to perform logical operations on data from multiple pages.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If three-dimensional NAND flash memory structure is used, then storage capacity is improved, but defect rate (open and short defects in memory holes) increases
Solution Approach 1:
The patent segments the ROM fuse information storage across multiple pages (first page, second page, third page) rather than storing it in a single location. This segmentation ensures that defects in one page do not compromise the entire ROM fuse information, allowing the system to maintain reliability while preserving the high storage capacity enabled by the three-dimensional structure.
Solution Approach 2:
The patent implements error correction mechanisms and redundancy by storing ROM fuse information across multiple pages before defects occur. The system includes circuits to read from multiple pages and perform majority logic operations, cushioning against the potential harm of open or short defects that may arise in the three-dimensional memory structure.
2Device complexity
If ROM fuse information is stored in single page, then device complexity is reduced, but error correction capability is insufficient
Solution Approach 1:
The patent divides the ROM fuse information into multiple pages (first, second, and third pages) to enhance error correction capability. By segmenting the stored information across separate physical pages, the system can read from multiple pages and use majority logic to correct errors, thereby improving reliability without requiring a completely complex rearchitecture.
Solution Approach 2:
The patent creates copies of ROM fuse information across multiple pages. The first, second, and third pages all contain ROM fuse information that can be used to reconstruct the complete set of fuse settings. This copying strategy enables error correction through redundancy while maintaining a relatively simple overall device structure.
3Measurement precision
If majority logic operation is implemented for error correction, then data read precision is improved, but arithmetic operation circuit complexity increases
Solution Approach 1:
The patent stores multiple copies of ROM fuse information across different pages, which enables the majority logic operation to function effectively. By having redundant copies, the circuit can compare values from the first, second, and third pages and determine the correct value, thereby improving data read precision through a relatively straightforward comparison and selection process.
Solution Approach 2:
The patent changes the storage parameter by distributing ROM fuse information across multiple pages rather than using a single page. This parameter change enables the majority logic operation to leverage redundancy for error correction, improving measurement precision while keeping the arithmetic operation circuit design manageable through systematic data organization.
Data Source
AI summary
According to one embodiment, a semiconductor memory device reads data in units of page. The device includes: a memory cell array; a plurality of latch circuits; and an arithmetic operation circuit. The memory cell array holds data multiplexed in at least three pages. The latch circuits read and hold the multiplexed data at a startup. The arithmetic operation circuit performs operations by use of the multiplexed data.