Memory Device GIDL Erase Voltage Control
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Solution Overview
Problem
Current memory devices face inefficiencies in performing Gate Induced Drain Leakage (GIDL)-based erase operations, particularly in terms of time required, erase stress, and power consumption, due to limitations in voltage management during the erase process.
Innovation Solution
The implementation of a memory device that applies two types of erase permission voltages with different potential levels to word lines during an erase operation, sequentially selecting word lines from the edge to the center of the memory block, and using a control circuit to manage these voltages, including a first erase permission voltage with a negative level lower than ground and a second erase permission voltage at ground level, to enhance hole mobility and reduce the need for incremental voltage increases.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If a single erase permission voltage is applied to all word lines during GIDL-based erase operation, then the device structure remains simple, but the erase operation time is long and power consumption is high
Solution Approach 1:
The patent divides the word lines into two groups: selected word lines (receiving first erase permission voltage) and unselected word lines (receiving second erase permission voltage). This segmentation allows different voltage levels to be applied to different regions, enabling faster erase operation in selected areas while maintaining manageable control complexity through systematic voltage distribution.
Solution Approach 2:
The patent applies different voltage levels (first erase permission voltage vs. second erase permission voltage) to different word lines based on their selection status. This local quality differentiation optimizes the erase operation by providing appropriate voltage conditions specifically where needed, improving overall erase speed without requiring complex global voltage management.
2Object-affected harmful factors
If high erase voltage is applied to all word lines simultaneously, then erase stress is high, but the device structure and control remain simple
Solution Approach 1:
The patent segments the word lines into selected and unselected groups, applying different voltage levels to each group. This reduces erase stress by avoiding uniform high voltage application across all word lines, while the systematic segmentation approach keeps voltage management complexity manageable through clear control logic.
Solution Approach 2:
The patent changes the voltage parameter (erase permission voltage level) based on the selection status of word lines. By dynamically adjusting voltage levels rather than applying constant high voltage, the patent reduces erase stress while maintaining effective erase operation in selected regions, with complexity managed through parameter-based control.
3Reliability
If incremental voltage increase (ISPE) is used to reduce erase stress, then device reliability improves, but the erase operation time increases significantly
Solution Approach 1:
The patent segments the erase operation into simultaneous voltage applications to selected and unselected word lines. This allows the erase process to proceed more efficiently than sequential ISPE methods, reducing total erase time while still managing voltage stress through differentiated voltage levels that protect device reliability.
Solution Approach 2:
The patent applies the first erase permission voltage to selected word lines and the second erase permission voltage to unselected word lines simultaneously from the beginning of the erase operation. This preliminary action eliminates the need for incremental voltage increases over time, significantly reducing erase operation time while maintaining device reliability through appropriate initial voltage distribution.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach significantly reduces the time needed for erase operations, minimizes erase stress, and decreases power consumption by optimizing voltage application, thereby improving the efficiency of the GIDL-based erase process.
Implementation Method 1
a memory device capable of efficiently performing a GIDL (Gate Induced Drain Leakage)-based erase operation
Data Source
AI summary
A memory device comprising: a plurality of memory blocks each including a plurality of word lines arranged between a first and second select line, a peripheral circuit performs an erase operation by applying an erase voltage to a source or drain line of a selected memory block, and a control logic controls, in a period in which the erase operation is performed, the peripheral circuit to: sequentially select the plurality of word lines included in the selected memory block at least one by one from a word line closest to the first and second select line to a word line farthest from the first and second select line, apply a first erase permission voltage to the selected word lines, and apply a second erase permission voltage, which have a higher potential level than the first erase permission voltage, to remaining word lines except the selected word lines.