Memory Device Global Line Groups Data Input Output
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Solution Overview
Problem
In memory devices, as the number of memory cells increases, the probability of data errors also rises, leading to higher bit error rates, and storing different-sized data in uniformly structured sub-memory cell arrays can reduce usable memory area and complicate layout due to varying sizes of information for error correction.
Innovation Solution
The memory device employs distinct global line groups for data input and output, allowing for different numbers of global lines for each group, enabling efficient data transmission and storage while optimizing layout and area usage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If sub memory cell arrays are made uniform in structure, then manufacturing and layout are simplified, but the usable memory area is reduced when storing data of various sizes
Solution Approach 1:
The memory device divides the memory cell array into multiple sub-memory cell arrays, each capable of storing different sizes of data. This segmentation allows each sub-array to be optimized for specific data sizes while maintaining overall structural simplicity through standardized interconnection components.
Solution Approach 2:
The patent implements a universal interconnection structure that can accommodate multiple data sizes. The standardized bit lines, sense amplifiers, and control logic can handle various data widths (e.g., 8-bit, 16-bit, 32-bit) without requiring completely separate circuitry for each size, thus maintaining layout simplicity while supporting variable data storage.
2Ease of manufacture
If sub memory cell arrays are made uniform in structure, then manufacturing is simplified, but the layout becomes complicated when accommodating varying data sizes
Solution Approach 1:
The patent applies local quality by allowing different sub-memory cell arrays to have different data storage capacities while maintaining uniform manufacturing processes. Each sub-array can be configured for specific data sizes (e.g., some arrays store 8-bit data, others store 16-bit data) while using the same fabrication steps and standardized interconnection components, thus simplifying manufacturing without excessive layout complexity.
3Quantity of substance
If the number of memory cells is increased, then memory capacity is improved, but the probability of data errors and bit error rate increase
Solution Approach 1:
The memory device segments the large memory cell array into multiple smaller sub-memory cell arrays. Each sub-array can be independently managed and protected, reducing the overall error probability. By dividing the memory space, the system can apply error correction codes more effectively to each segment rather than attempting to protect a single large array.
Data Source
AI summary
A memory device includes first, second, third, and fourth memory cell groups and first and second transmitters. The first and second memory cell groups share first local lines. The third and fourth memory cell groups share second local lines. The first transmitter transmits first data to first global lines based on a read command. The first data is output from one of the first memory cell group and the second memory cell group on the first local lines. The second transmitter transmits second data to second global lines based on the read command. The second data is output from one of the third memory cell group and the fourth memory cell group on the second local lines. The number of the first global lines is different from the number of the second global lines.