Vertical Memory Device Integration via Segmented Ground Select Lines
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
The increasing demand for high-capacity data processing in electronic products necessitates higher semiconductor memory device integration, which existing memory devices with planar transistor structures struggle to achieve effectively.
Innovation Solution
A memory device design featuring a pair of common source lines, ground select lines, word lines, and separation insulating patterns, along with a dummy channel structure, to enhance integration and reliability, particularly using a vertical transistor structure.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If planar transistor structures are used, then manufacturing is simpler, but integration density is limited
Solution Approach 1:
The patent transitions from planar (2D) transistor structures to vertical (3D) transistor structures, stacking multiple transistor layers vertically above the substrate. This dimensional change enables significantly higher integration density by utilizing the third dimension (height) rather than only the planar area, allowing more memory cells to be packed into the same footprint while maintaining manufacturing feasibility through established vertical deposition and etching processes
2Quantity of substance
If vertical transistor structures are used to increase integration, then integration density improves, but read disturb increases
Solution Approach 1:
The patent divides the ground select lines into multiple segments separated by first separation insulating patterns along the first direction. This segmentation isolates adjacent ground select line segments, preventing charge leakage and reducing read disturb effects between neighboring memory cell strings, thereby improving reliability while maintaining the high integration density of vertical structures
Solution Approach 2:
The patent introduces first separation insulating patterns as intermediary structures between adjacent ground select lines. These insulating patterns act as mediators that electrically isolate the ground select lines, preventing unwanted charge coupling and reducing read disturb while allowing the ground select lines to maintain their functional proximity for compact design
3Quantity of substance
If ground select lines are placed close together to increase integration, then integration density improves, but structural stability deteriorates
Solution Approach 1:
The patent introduces dummy channel structures as intermediary support elements positioned between adjacent ground select lines. These dummy channel structures provide mechanical support and spacing, maintaining structural stability and preventing deformation of the closely-spaced ground select lines while allowing sufficient integration density through optimized vertical stacking and horizontal spacing
Data Source
AI summary
A memory device includes a pair of common source lines disposed on a substrate spaced apart from each other and extended in a first direction; a plurality of ground select lines disposed between the pair of common source lines, extended in the first direction, and disposed on the same level; a plurality of word lines disposed on the plurality of ground select lines between the pair of common source lines, extended in the first direction, and disposed on the same level, at least a portion of the plurality of word lines being connected by a connection electrode; and a plurality of first separation insulating patterns disposed between individual ground select lines of a portion of the plurality of ground select lines and extended in the first direction. The at least portion of the plurality of word lines is connected by a connection electrode.