Memory Device High-k Metal Gate Mask Reduction
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Solution Overview
Problem
The semiconductor industry faces challenges in reducing the number of masks required for fabricating memory devices with high-k metal gate structures, which affects the efficiency and complexity of the manufacturing process.
Innovation Solution
The implementation of high-k metal gate structures in logic and storage transistors, along with a method that includes forming logic and memory well regions, charge storage structures, and high-k dielectric layers, reduces the number of masks needed by integrating these components into a semiconductor substrate through specific fabrication steps.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If conventional fabrication processes are used for memory devices with high-k metal gate structures, then the manufacturing process requires multiple masks, but this increases the complexity and reduces the efficiency of the manufacturing process
Solution Approach 1:
The patent merges the formation of logic and memory well regions into a single fabrication process using a unified mask pattern. The method combines multiple previously separate masking steps into one integrated process where the same mask defines both logic transistor gates and memory transistor structures, thereby reducing the total number of masks required while maintaining the ability to form distinct functional regions with different doping profiles
Solution Approach 2:
The patent makes the mask pattern universal by designing it to serve multiple functions simultaneously: it defines logic transistor gates, memory transistor gates, and charge storage structure alignment all in one step. This multi-functional mask approach allows a single mask layer to control the formation of different device types with different requirements, eliminating the need for separate specialized masks for each function
2Productivity
If the number of masks is reduced in fabrication, then manufacturing efficiency is enhanced, but the precision of forming distinct logic and memory regions may be compromised
Solution Approach 1:
The patent applies local quality by using a single mask pattern that creates different local outcomes through selective doping processes. The mask defines regions that subsequently receive different dopant types and concentrations, allowing precise local differentiation of logic and memory regions. The same mask structure serves as a template for creating locally distinct electrical properties through controlled ion implantation or diffusion steps that follow the masking
Data Source
AI summary
A memory device includes a semiconductor substrate, a logic transistor, and a storage transistor. The semiconductor substrate has a logic region and a memory region. The logic transistor is disposed on the logic region, in which the logic transistor comprises a high-k metal gate structure. The storage transistor is disposed on the memory region, in which the storage transistor includes a charge storage structure and a high-k metal gate structure. The charge storage structure is disposed on the memory region. The high-k metal gate structure is disposed on the charge storage structure.