Memory Device Host Memory Buffer Power State Transitions

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Solution Overview

Problem

Memory devices face high latency and power consumption challenges when transitioning between power states, particularly when moving to lower-power states like PS4, due to the need to write and read operating state information from non-volatile memory, which increases transition latency and power consumption.

Innovation Solution

The use of host memory resources to efficiently transition between power states by allocating a host memory buffer for storing resume data, allowing the memory device to read this data directly upon resuming without needing to retrieve it from non-volatile memory, thus reducing latency and power consumption.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If operating state information is written to non-volatile memory during power state transitions, then data persistence is ensured, but transition latency increases

Engineering Contradiction:

Improvedata persistenceVSAvoidtransition latency

Core Design Contradiction:

ReliabilityVSLoss of time

Solution Approach 1:

The host system performs preliminary actions by allocating and preparing host memory buffers before the memory device needs to transition to low-power states. The host memory is pre-configured to store resume data structures that will be needed during power state transitions, eliminating the need to access non-volatile memory during the actual transition process.

Inventive Principle:

Principle #10Preliminary action

Solution Approach 2:

Host memory serves as an intermediary between the memory device and non-volatile memory during power state transitions. Instead of directly accessing non-volatile memory for resume data, the system uses host memory as a intermediate storage layer that can be quickly accessed during transitions while still maintaining data persistence through the host system's memory management.

Inventive Principle:

Principle #24Intermediary (Mediator)

2Reliability

If operating state information is read from non-volatile memory during resume, then data integrity is maintained, but power consumption increases

Engineering Contradiction:

Improvedata integrityVSAvoidpower consumption

Core Design Contradiction:

ReliabilityVSUse of energy by moving object

Solution Approach 1:

Inventive Principle:

Principle #10Preliminary action

Solution Approach 2:

The system creates copies of resume data structures in host memory that can be quickly accessed during power state transitions. Instead of repeatedly accessing non-volatile memory, the host memory contains replicated copies of the necessary state information, reducing both access time and power consumption during transition operations.

Inventive Principle:

Principle #26Copying

3Speed

If on-board DRAM is used to maintain operating state, then rapid transitions are enabled, but device cost increases

Engineering Contradiction:

Improvetransition speedVSAvoiddevice cost

Core Design Contradiction:

SpeedVSDevice complexity

Solution Approach 1:

The host memory serves multiple functions: it acts as general system memory for the host computing system while simultaneously serving as fast resume data storage for the memory device during power state transitions. This multi-functionality eliminates the need for dedicated on-board DRAM in the memory device, reducing device cost while maintaining rapid transition capability.

Inventive Principle:

Principle #6Universality (Multi-functionality)

Solution Approach 2:

The host computing system provides the memory device with fast resume data access using the host's own memory resources. Instead of requiring the memory device to have its own expensive on-board DRAM, the memory device leverages the host system's memory infrastructure, allowing the host to service the memory device's resume needs using shared resources.

Inventive Principle:

Principle #25Self-service

Data Source

PatentUS10725677B2Systems and methods for efficient power state transitions

Publication Date: 2020.07.28 SANDISK TECHNOLOGIES LLC

AI summary

A memory device may be configured to leverage memory resources of a host computing device to efficiently transition between different power states. In some embodiments, the memory device stores resume data within a host memory buffer (HMB) before transitioning to a low-power state, and uses the resume data stored within the HMB to resume operation from the low-power state. The memory device may be configured to pre-populate the HMB with resume data prior to transitioning to the low-power state. In some embodiments, the disclosed memory device is configured to gradually resume from the low-power state, which may comprise resuming services of the memory device in the order such services are required during the resume process.