Semiconductor Memory Device Shallow Deep Hole Formation
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Solution Overview
Problem
Current semiconductor memory devices face challenges in achieving high integration of memory cell arrays due to limitations in hole formation and semiconductor layer formation processes, which affect the density and depth of memory cells, leading to reduced performance and integration capabilities.
Innovation Solution
The semiconductor memory device employs a specific manufacturing method involving the formation of shallow and deep holes (STH_Ba and STH_Fa) in the second chip, allowing for the preferential formation of semiconductor layers and conductive layers, and the use of direct bonding between chips to enhance integration, while also optimizing the structure of memory planes and peripheral circuits.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If conventional hole formation and semiconductor layer formation processes are used, then the manufacturing process is simple, but the memory cell density and depth are limited
Solution Approach 1:
The patent segments the hole formation process into two distinct stages: shallow hole formation (STH_Ba) and deep hole formation (STH_Fa). This segmentation allows each process to be optimized independently, with shallow holes formed first to a controlled depth, followed by deep holes extending further into the substrate. This resolves the contradiction by enabling greater memory cell depth and density without requiring a complete redesign of the entire formation process.
Solution Approach 2:
The patent introduces a vertical dimensionality aspect by forming holes at different depths (shallow vs. deep) and utilizing stacked structures with multiple memory planes. This dimensional approach allows memory cells to be arranged in three-dimensional configurations, increasing storage density without proportionally increasing the footprint area, thus resolving the density limitation while maintaining process feasibility.
2Quantity of substance
If memory cell arrays are highly integrated, then storage capacity increases, but the number of stacked structures must be reduced
Solution Approach 1:
The patent implements a nested structure where memory cell arrays are organized into multiple stacked memory planes (first memory plane and second memory plane) that are vertically integrated. Each plane contains memory cells formed in different hole depths, creating a nested arrangement where shallow and deep holes coexist within the same vertical stack. This nesting enables high storage capacity while maintaining a compact stacked structure, resolving the contradiction between integration and structure reduction.
Solution Approach 2:
The patent applies preliminary action by forming the shallow holes (STH_Ba) and their associated semiconductor layers before forming the deep holes (STH_Fa). This sequential approach ensures that the shallow structure is established first, providing a foundation for subsequent deep hole formation. This preliminary action allows both shallow and deep memory cells to coexist in the final stacked structure, maximizing storage capacity without compromising structural integrity.
3Manufacturing precision
If chip bonding is used to connect memory cell arrays, then integration is improved, but bonding area and complexity increase
Solution Approach 1:
The patent merges the memory cell array formation and chip bonding processes by integrating multiple memory planes onto a single semiconductor substrate before final chip assembly. The first and second memory planes are formed and connected through shared bonding electrodes and conductive layers, reducing the need for separate bonding operations. This merging approach improves integration while minimizing the bonding area required, as connections are established within the stacked structure rather than through extensive external bonding.
Data Source
AI summary
A semiconductor memory device includes a first chip and a second chip. The first chip includes a semiconductor substrate and a plurality of transistors disposed on a surface of the semiconductor substrate. The second chip includes a plurality of first conductive layers, a plurality of first semiconductor layers, and a plurality of memory cells disposed in intersection portions of the plurality of first conductive layers and the plurality of first semiconductor layers. The second chip includes a second semiconductor layer farther from the semiconductor substrate than the plurality of first conductive layers. The second semiconductor layer is connected to the plurality of first semiconductor layers and a first insulating layer that includes a part farther from the semiconductor substrate than a surface on a side opposite to the semiconductor substrate of the second semiconductor layer and a part closer to the semiconductor substrate than the surface.