Semiconductor Memory Device High Voltage Path Segmentation
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Solution Overview
Problem
Existing semiconductor memory devices face limitations in the number of simultaneously writable memory cell transistors due to increased voltage drop in high voltage supply paths, requiring larger circuit areas to reduce impedance, which restricts the number of transistors that can be written simultaneously.
Innovation Solution
A semiconductor memory device with a high voltage generation circuit and a high voltage switching circuit that includes a third switch to directly supply high voltage to the source line without going through the high voltage switching circuit, along with a latch circuit configuration using CMOS inverters and MOS transistors to manage write and erase operations, allowing for increased writing current and reduced circuit area.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the number of simultaneously writable memory cell transistors is increased, then the writing capability is improved, but the voltage drop in the high voltage supply path increases
Solution Approach 1:
The invention divides the high voltage supply path into two separate paths: one path through the high voltage switching circuit for erase operations, and another direct path through the third switch for write operations. This segmentation allows write operations to bypass the impedance of the high voltage switching circuit, reducing voltage drop and enabling more memory cell transistors to be written simultaneously.
2Loss of energy
If the circuit area is increased to reduce impedance, then the voltage drop is reduced, but the device area increases
Solution Approach 1:
The invention extracts the write operation path from the high voltage switching circuit by introducing a third switch that directly connects the high voltage generation circuit to the source line. This separation removes the impedance bottleneck caused by the high voltage switching circuit transistors, allowing sufficient writing current without increasing circuit area.
3Loss of energy
If larger transistors are used in the high voltage switching circuit to reduce impedance, then the voltage drop is reduced, but the circuit area increases
Solution Approach 1:
The invention dynamically routes the high voltage supply based on the operation type: during write operations, the third switch is activated to provide a direct low-impedance path, while during erase operations, the high voltage switching circuit is used. This dynamic switching allows the use of smaller transistors in the high voltage switching circuit without compromising write capability.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration minimizes circuit area and reduces voltage drop in the high voltage supply path, enabling multi-bit simultaneous writing by ensuring most of the writing current flows through a dedicated transfer gate, thereby increasing the number of writable memory cell transistors.
Implementation Method 1
a high voltage generation circuit generating a high voltage for erasing and writing data
Implementation Method 2
a predetermined high voltage (e.g. 13V) is applied to the control gate 109 to flow a Fowler-Nordheim tunneling current through the tunnel insulation film 108
Implementation Method 3
a high voltage (e.g. 10V) is applied to the source 103 to flow a current through the channel 104, and thereby channel hot electrons are injected into the floating gate 106 through the gate insulation film 105
Data Source
AI summary
The invention provides a semiconductor memory device where a circuit area is minimized and a voltage drop in a high voltage supply path to a source line is reduced. An output of a high voltage generation circuit is connected to a source line through a first transfer gate, and connected to a word line through a second transfer gate. The first transfer gate is configured of a P-channel type MOS transistor of which on and off are controlled by a write enable signal, and the second transfer gate is configured of a P-channel type MOS transistor of which on and off are controlled by an erase enable signal. A third transfer gate supplying the output of the high voltage generation circuit to the source line without through a high voltage switching circuit is further provided. The third transfer gate is configured of a P-channel type MOS transistor and an inverted output of the high voltage switching circuit is applied to the gate thereof.