Stacked Memory Device Insulating Substrate From Bottom Conductive Layer
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Solution Overview
Problem
Traditional non-volatile memory (NVM) devices with vertical channels face issues of high power consumption and reliability due to parasitic junctions and signal interference, and they occupy large chip areas because the substrate serves as both the bottom common source line and the silicon substrate.
Innovation Solution
A memory device design where the peripheral circuit portion and array portion are stacked, with a bottom conductive layer electrically insulated from the semiconductor substrate, allowing for improved control over the electrical characteristics of the substrate through a multilayers stack and channel layer configuration, reducing chip area and enhancing operation reliability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If the substrate serves as the bottom common source line in traditional NVM devices, then the device structure is simplified, but parasitic junctions occur between the doped region and semiconductor substrate, increasing power consumption and deteriorating program/read operation reliability and device speed
Solution Approach 1:
The invention segments the substrate and bottom common source line into separate components. The substrate remains as the semiconductor base while the bottom common source line is formed as a distinct conductive layer (first conductive layer) separated from the substrate by an isolation layer. This segmentation eliminates parasitic junctions between the doped region and semiconductor substrate, resolving the contradiction between structural simplicity and operational reliability.
Solution Approach 2:
The invention introduces an isolation layer as an intermediary component between the substrate and the bottom common source line. This isolation layer prevents direct electrical contact that would create parasitic junctions, thereby improving program/read operation reliability while maintaining the functional separation of substrate and source line.
2Reliability
If the substrate serves as the bottom common source line with a doped region, then electrical connection is achieved, but high resistance is formed in the bottom common source line, increasing power consumption
Solution Approach 1:
The invention changes the electrical parameters of the bottom common source line by forming it as a separate conductive layer with optimized material composition and doping characteristics. This allows the bottom common source line to achieve lower resistance compared to using the substrate directly, thereby reducing power consumption during erase operations while maintaining reliable electrical connection.
3Ease of manufacture
If the array portion and peripheral circuit portion are arranged side by side on the same plane in traditional NVM devices, then manufacturing is simplified, but the chip area is too large
Solution Approach 1:
The invention transitions from a planar two-dimensional layout to a three-dimensional stacked architecture. The array portion is positioned above the peripheral circuit portion, utilizing the vertical dimension to reduce chip area. This dimensional change allows both portions to coexist in a compact footprint while maintaining manufacturing feasibility through sequential fabrication processes.
4Ease of operation
If the substrate serves as the bottom common source line, then block erase operation is enabled through the channel layer, but signal interference and RC delay occur due to parasitic junction capacitance, deteriorating device speed
Solution Approach 1:
The invention extracts the parasitic junction capacitance from the system by separating the bottom common source line from the substrate. The isolation layer removes the parasitic junction that causes RC delay and signal interference, thereby improving device speed while preserving the block erase operation functionality through the channel layer.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution reduces chip area, improves operation reliability, and enhances erase and read functions by controlling the electrical potential of the semiconductor substrate, thereby reducing power consumption and signal interference.
Implementation Method 1
The bottom conductive layer and the semiconductor layer are electrically insulated by the isolation layer
Implementation Method 2
adjusting an electrical character of the semiconductor substrate by controlling an electrical potential of the bottom conductive layer
Data Source
AI summary
A memory device includes a peripheral circuit portion and an array portion disposed on the peripheral circuit portion. The array portion includes a bottom conductive layer; an isolation layer disposed on the bottom conductive layer; a semiconductor substrate disposed on the isolation layer; a channel layer disposed on a sidewall of a first through opening which exposes the semiconductor substrate and electrically contacting the semiconductor substrate; a memory layer; and a multilayers stack disposed on the semiconductor substrate. The multilayers stack includes a first insulating layer disposed on the semiconductor substrate; a first conductive layer disposed on the first insulating layer; second insulating layers disposed over the first insulating layer; and second conductive layers alternatively stacked with the second insulating layers and insulated from the first conductive layer. The memory layer is disposed between the channel and first conductive layers, and between the channel and second conductive layers.