Semiconductor Memory Device Independent Power Interconnect Segmentation
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Solution Overview
Problem
Semiconductor memory devices, particularly NAND flash memories, face challenges in maintaining operational reliability due to voltage drops and timing deviations in output signals caused by shared power supply interconnects, which can lead to delays and reliability issues as clock signal frequencies increase.
Innovation Solution
The semiconductor memory device configuration includes independent coupling of circuit units to distinct interconnects for power supply and ground voltage, preventing voltage drops and fluctuations, thereby maintaining consistent signal timing across output circuits.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If multiple circuit units share common power supply interconnects, then device complexity is reduced, but voltage drops and timing deviations occur leading to reliability degradation at high clock frequencies
Solution Approach 1:
The patent divides the common power supply interconnect into multiple separate interconnects, with each circuit unit having its own dedicated power supply and ground interconnects. This segmentation eliminates voltage drops and timing deviations caused by shared interconnects, thereby improving operational reliability at high clock frequencies despite increasing device complexity.
2Productivity
If clock signal frequency is increased to improve productivity, then output speed increases, but voltage drops cause timing deviations and reliability issues
Solution Approach 1:
By segmenting the power supply distribution into dedicated interconnects for each circuit unit, the patent eliminates voltage drops that cause timing deviations. This allows the system to operate at higher clock frequencies and achieve greater productivity while maintaining signal timing reliability.
Data Source
AI summary
According to one embodiment, a semiconductor memory device includes: first and second circuit units, a driver circuit, an input/output pad, first and second power supply pads, and first and second interconnects. The first interconnect is configured to provide coupling between the first circuit unit and the first power supply pad. The second interconnect is configured to provide coupling between the second circuit unit and the first power supply pad and have no electrical coupling to the first interconnect.