3D Memory Device Vertical Interconnection Area Reduction
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Solution Overview
Problem
In three-dimensionally arranged memory devices, the surface area of connection regions is typically large, limiting memory capacity due to the need for extensive interconnection and insulation structures, which hampers the efficient packing of memory cells and increases the size of the connection region at the expense of the memory region.
Innovation Solution
The memory device design incorporates a connection region surrounded by a memory region with an insulating body and contact plugs extending through it, reducing the surface area required for connections by using an interconnection layer that electrically connects electrode and semiconductor layers, thereby minimizing the space needed for hook-up regions and increasing the memory cell area.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If the surface area of connection region is reduced, then memory capacity is improved, but the complexity of interconnection structures increases
Solution Approach 1:
The patent transitions from planar two-dimensional interconnection to three-dimensional vertical interconnection by stacking electrode layers and semiconductor layers in the thickness direction. Contact plugs extend vertically through insulating layers to connect stacked memory cells, enabling memory capacity expansion without increasing surface area of connection regions.
Solution Approach 2:
The patent implements nested structures where contact plugs are embedded within insulating layers, and multiple electrode layers and semiconductor layers are stacked within a vertical columnar structure. This nesting allows multiple memory cells to be integrated in a three-dimensional space above the connection region, reducing the surface footprint while maintaining connectivity.
2Area of stationary object
If the surface area of connection region is reduced, then memory region area is increased, but manufacturing precision requirements increase
Solution Approach 1:
The patent divides the memory device into distinct functional regions: connection regions for electrical connectivity and memory regions for data storage. By segmenting these functions spatially and using vertical stacking, the memory region surface area is maximized while connection regions are minimized to only where vertical contacts are needed, reducing the trade-off between area and precision.
Solution Approach 2:
The patent moves interconnection functions from the surface plane to the vertical dimension through stacked layers and contact plugs. This dimensional transition reduces the surface area occupied by connection structures, expanding memory region area while concentrating precision requirements into controlled vertical alignment of contact plugs with underlying electrodes.
Data Source
AI summary
A memory device includes a memory region, a connection region, an interconnection layer and a circuit. The memory region includes electrode layers and semiconductor layers. The electrode layers are stacked in a first direction, and the semiconductor layers extend in the first direction through the electrode layers. The connection region is surrounded with the memory region, and includes an insulating body and contact plugs. The insulating body has a thickness in the first direction thicker than a stacked width in the first direction of the electrode layers, and the contact plugs extending in the first direction through the insulating body. The interconnection layer includes interconnections electrically connected respectively to the electrode layers and some of the semiconductor layers. The electrode layers and the insulating body are positioned between the circuit and the interconnection layer in the first direction.