Memory Device Internal Data Signal Generation for Pin-Limited Testing
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Solution Overview
Problem
The limited number of input and output pins in parallel test systems for dynamic random access memories (DRAMs) leads to a decrease in the number of pins allocated for data signal transmission, resulting in undetected defects during memory device testing.
Innovation Solution
A memory device comprising a controller, multiplexer, deserializer, data modifier, and error detector that generates internal data signals using a clock signal without an external data signal, allowing for error detection and data modification within the memory cell array.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the number of DRAMs to be tested is increased in a parallel test system, then productivity is improved, but the number of pins allocated for data signal transmission decreases
Solution Approach 1:
The patent uses a clock signal as a template or copy to generate multiple internal data signals (first to M-th internal data signals) through the multiplexer. Instead of requiring external data signals for each DRAM, the system creates internal copies of the clock signal that are then deserialized and modified to serve as test data, reducing the need for external data pins while maintaining comprehensive testing capability
Solution Approach 2:
The memory device performs self-testing by generating its own internal data signals using the clock signal and internal components (multiplexer, deserializer, data modifier). The device uses its own resources to create test patterns without relying on external data signal inputs, enabling autonomous defect detection across all data lines
2Quantity of substance
If only some data signals are used to test DRAM operation, then the number of pins required is reduced, but certain defects may not be detected
Solution Approach 1:
The patent dynamically routes the clock signal through the multiplexer to generate multiple different internal data signals that can be distributed to different DRAMs. The multiplexer dynamically selects and distributes clock signal copies to various deserializers, which then generate diverse test patterns ensuring all data lines are tested comprehensively despite using minimal external pins
Solution Approach 2:
The patent segments the single clock signal into multiple separate internal data signal streams through the multiplexer and deserializer combination. Each DRAM receives a segmented portion of the clock signal that is then deserialized into multiple bit lines, ensuring comprehensive coverage of all data lines while using only a few external pins
Data Source
AI summary
A memory device includes a controller, a multiplexer, a deserializer, a data modifier, a memory cell array and an error detector. The controller is configured to generate signals in response to an address signal and a command signal. The multiplexer is configured to output a clock signal as internal data signals when the test mode signal is activated. The deserializer is configured to deserialize N bit values included in the internal data signals to generate deserialized signals. The data modifier is configured to invert the deserialized signals to generate bit line signals in response to an inversion control signal and the data modifying signals. The memory cell array is configured to store the bit line signals to memory cells corresponding to the address signal. The error detector is configured to determine if an error exists in signals read from the memory cells and to output an error detecting signal.