Semiconductor Memory Device Unused I/O Pad Power Stabilization

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Solution Overview

Problem

Conventional semiconductor memory devices have low use efficiency of data I/O pads, leading to increased power noise due to unused pads being in a no connection state, which affects system operation, especially at lower power supply voltages.

Innovation Solution

Connecting unused data I/O pads to power or ground pins, utilizing NMOS or PMOS transistors to selectively activate pads based on data bit organization, allowing these pads to stabilize and strengthen the power supply or ground voltage levels when not used for data transfer.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Device complexity

If data I/O pads are left in no connection state for unused organizations, then device complexity is reduced, but power noise increases and power stability deteriorates

Engineering Contradiction:

Improvebonding configuration complexityVSAvoidpower stability

Core Design Contradiction:

Device complexityVSReliability

Solution Approach 1:

The data I/O pads are designed to serve multiple functions: they can be used for data input/output in specific organizations or connected to power pins to strengthen power supply in other organizations. This multi-functionality resolves the contradiction by allowing the same pads to contribute to either data transmission or power stability depending on the operational mode.

Inventive Principle:

Principle #6Universality (Multi-functionality)

Solution Approach 2:

The unused data I/O pads are made to serve the power system by connecting them to power pins, allowing them to strengthen the power supply network. Instead of being completely idle, these pads actively contribute to power stability, thus resolving the contradiction between simplicity and reliability.

Inventive Principle:

Principle #25Self-service

2Adaptability or versatility

If data I/O pads are connected to data input/output pins for all organizations, then adaptability is improved, but power noise increases due to unused pads

Engineering Contradiction:

Improvedata bit organization adaptabilityVSAvoidpower noise

Core Design Contradiction:

Adaptability or versatilityVSObject-affected harmful factors

Solution Approach 1:

The bonding configuration is made dynamic by allowing different connection states for different organizations. The pads can be selectively connected to data pins or power pins based on the operational organization, enabling the system to adapt its configuration to minimize power noise while maintaining versatility.

Inventive Principle:

Principle #15Dynamics

Solution Approach 2:

Different connection qualities are applied to different pads based on their usage status. Used pads are connected to data pins for high-speed data transmission, while unused pads are connected to power pins to provide local power strengthening, thus reducing power noise without sacrificing adaptability.

Inventive Principle:

Principle #3Local quality

3Use of energy by moving object

If power supply voltage is reduced to improve energy efficiency, then energy consumption is reduced, but power noise becomes more significant

Engineering Contradiction:

Improvepower consumptionVSAvoidpower noise effect

Core Design Contradiction:

Use of energy by moving objectVSObject-affected harmful factors

Solution Approach 1:

The previously harmful effect of unused pads (creating power noise) is converted into a benefit by connecting them to power pins. This transformation allows the same pads to become power strengthening elements, which helps counteract the increased power noise effect that occurs at lower supply voltages.

Inventive Principle:

Principle #22Blessing in disguise (Convert harm into benefit)

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This approach enhances the power stability and reduces power noise in semiconductor memory devices by effectively utilizing previously unused pads, improving the operational reliability across different data bit organizations.

Implementation Method 1

an NMOS transistor 33 for the purpose of electrostatic discharge (ESD) protection, which is connected between the pad PAD_UDQ and a ground voltage line VSS

Methodology Applied

Scientific EffectElectrostatic Discharge: Electrostatic Discharge

Implementation Method 2

a PMOS transistor connected between the data input/output pad and a power supply voltage line

Methodology Applied

Scientific EffectElectrical Conduction: Conduction (electrical)

Data Source

PatentUS7518898B2Semiconductor memory device with strengthened power and method of strengthening power of the same

Publication Date: 2009.04.14 SAMSUNG ELECTRONICS CO LTD

AI summary

In a semiconductor memory device the power level of which is strengthened by using data input/output pads in a no connection state, and a method of strengthening the power of the semiconductor memory device at a stabilized power level, the semiconductor memory device comprises: a plurality of data input/output drivers; and a plurality of data input/output pads, each connected to a corresponding one of the plurality of data input/output drivers. A first subset of the data input/output pads are connected to respective data input/output pins of a package, and several or all of a remaining subset of the data input/output pads that are not connected to data input/output pins of the package are connected to power pins of the package.