Memory Device Isolation Insulating Layer Word Line Segmentation
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Solution Overview
Problem
The challenge in memory device fabrication is to reduce the aspect ratio of unit cell regions and minimize misalignment of contacts connected to channel areas, while increasing the degree of integration in semiconductor devices, which is essential for smaller electronic products processing larger data amounts.
Innovation Solution
A memory device is designed with a substrate having common source regions and channel structures, where an isolation insulating layer, formed from a sacrificial layer with a lower etching rate, divides conductive electrode layers into electrically separate portions, reducing the aspect ratio and misalignment by retaining a portion of the sacrificial layer to form a gate electrode layer and divide the word line.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If the degree of integration is increased to reduce overall device size, then smaller electronic products can process larger data amounts, but the aspect ratio of unit cell regions increases and manufacturing precision deteriorates
Solution Approach 1:
The patent divides the continuous word line into multiple segmented portions using isolation insulating layers formed from sacrificial layers. This segmentation allows each unit cell region to be independently structured, reducing the effective aspect ratio and improving alignment precision while maintaining high integration density through vertical stacking of channel structures and electrode layers.
Solution Approach 2:
The patent introduces sacrificial layers as intermediary structures that are selectively retained to form isolation insulating layers. These intermediary structures facilitate the division of word lines and reduction of aspect ratios during fabrication, and are subsequently removed or transformed, enabling improved manufacturing precision without compromising integration density.
2Manufacturing precision
If the aspect ratio of unit cell regions is reduced to improve manufacturing precision, then contact alignment is improved, but device complexity increases due to additional isolation structures
Solution Approach 1:
The sacrificial layers serve multiple functions: they act as placeholders during fabrication, are selectively retained to form isolation insulating layers that divide word lines, and ultimately contribute to reducing aspect ratios. This multi-functionality reduces overall device complexity by eliminating the need for separate isolation structures.
Solution Approach 2:
The patent changes the etching rate parameter of specific sacrificial layers to be lower than other sacrificial layers, enabling selective retention during fabrication. This parameter change allows the formation of isolation insulating layers without adding complex structural elements, improving contact alignment while maintaining manageable device complexity.
3Ease of manufacture
If sacrificial layers are completely removed to simplify fabrication, then manufacturing process is simplified, but word line division and aspect ratio reduction cannot be achieved
Solution Approach 1:
The patent applies different etching rates to different sacrificial layers, creating local quality differences. Specifically, the sacrificial layer forming the isolation insulating layer has a lower etching rate than other sacrificial layers, allowing it to be selectively retained in certain regions while other sacrificial layers are completely removed. This local differentiation enables both fabrication simplicity and aspect ratio control.
Solution Approach 2:
The patent performs preliminary action by forming isolation insulating layers from selectively retained sacrificial layers before completing the fabrication of other device components. This preliminary structuring establishes the word line divisions and aspect ratio reductions early in the process, simplifying subsequent fabrication steps while maintaining manufacturing precision.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances the integration density and manufacturing yield by reducing the aspect ratio of unit cell regions and minimizing contact misalignment, facilitating easier fabrication and improved performance in memory devices.
Implementation Method 1
The portion of the sacrificial layer defining the isolation insulating layer may include a material having a lower etching rate than other sacrificial layers used in the stack structure
Data Source
AI summary
A memory device includes a substrate having common source regions thereon, common source lines extending along a surface of the substrate and contacting the common source regions, respectively, and channel structures extending away from the surface of the substrate between the common source lines. The common source lines define a unit cell of the memory device therebetween. The memory device further includes an electrode stack structure having interlayer insulating layers and conductive electrode layers that are alternately stacked along sidewalls of the channel structures. The conductive electrode layers define respective gates of selection transistors and memory cell transistors of the memory device. An isolation insulating layer, which includes a portion of a sacrificial layer, is disposed between adjacent ones of the interlayer insulating layers in the stack structure. The isolation insulating layer divides at least one of the conductive electrode layers in the stack structure into electrically separate portions.