Memory Device Key-Value Pair Set Replacement

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Solution Overview

Problem

Existing memory devices face significant challenges with write amplification during garbage collection operations in log structured merge (LSM) key-value databases, leading to increased power consumption and reduced lifespan due to the need to rewrite large amounts of data.

Innovation Solution

The memory device employs a method to selectively replace the oldest key-value pair set with a new one, rewriting only unique data and avoiding the rewriting of duplicate keys, thereby reducing write amplification. This approach involves identifying duplicate keys, forming a new key-value pair set that excludes these duplicates, and replacing the oldest key-value pair set with the new one.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If garbage collection operations rewrite all data in key-value pair sets, then data consistency is maintained, but write amplification increases and power consumption rises

Engineering Contradiction:
Improvedata consistencyVSAvoidpower consumption
Core Design Contradiction:
ReliabilityVSLoss of energy

Solution Approach 1:

The patent extracts and identifies duplicate keys from key-value pair sets during garbage collection operations. By separating duplicate keys from unique keys, the system only rewrites the unique portion of data, thereby maintaining data consistency while significantly reducing the amount of data that needs to be rewritten, which directly lowers power consumption and write amplification.

Inventive Principle:
Principle #2Taking out (Extraction)

2Reliability

If garbage collection operations rewrite all data in key-value pair sets, then data consistency is maintained, but memory device lifespan is reduced

Engineering Contradiction:
Improvedata consistencyVSAvoidmemory device lifespan
Core Design Contradiction:
ReliabilityVSDuration of action of stationary object

Solution Approach 1:

The patent extracts duplicate keys from key-value pair sets and identifies only the unique keys that need to be rewritten. This selective rewriting approach maintains data consistency while reducing the total number of write operations on the memory device. Fewer write operations directly translate to reduced wear and tear on memory cells, thereby extending the overall lifespan of the memory device.

Inventive Principle:
Principle #2Taking out (Extraction)

3Productivity

If duplicate keys are identified and excluded from rewriting, then write amplification is reduced, but processing complexity increases

Engineering Contradiction:
Improvewrite amplificationVSAvoidprocessing complexity
Core Design Contradiction:
ProductivityVSDevice complexity

Solution Approach 1:

The patent performs preliminary identification and extraction of duplicate keys from key-value pair sets before the actual rewriting operation. By pre-processing the data to separate duplicates from uniques, the system simplifies the subsequent rewriting step to only handle unique keys. This preliminary action reduces write amplification while the structured approach to duplicate detection keeps processing complexity manageable.

Inventive Principle:
Principle #10Preliminary action

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This solution effectively reduces write amplification, minimizing wear and tear on the memory device and extending its lifespan while also lowering power consumption.

Implementation Method 1

applying a high positive voltage, which may be referred to as a 'program voltage,' a 'programming power voltage,' or 'VPP,' to a control gate to generate Fowler-Nordheim tunneling (referred to as 'F-N tunneling') between a floating gate and the semiconductor substrate. When F-N tunneling is occurring, electrons of the bulk area are accumulated on the floating gate by an electric field of VPP applied to the control gate to increase a threshold voltage of the memory cell.

Methodology Applied
Scientific EffectFowler-Nordheim tunneling:

Implementation Method 2

An erasing operation of the memory cell is concurrently performed in units of sectors sharing the bulk area (referred to as 'blocks'), by applying a high negative voltage, which may be referred to as an 'erase voltage' or 'Vera,' to the control gate and a configured voltage to the bulk area to generate the F-N tunneling. In this case, electrons accumulated on the floating gate are discharged into the source area, so that the memory cells have an erasing threshold voltage distribution.

Methodology Applied
Scientific EffectFowler-Nordheim tunneling:

Data Source

PatentUS20250156088A1Replacing key-value pair sets with new key-value pair sets
Publication Date: 2025.05.15 MICRON TECHNOLOGY INC
  • US20250156088A1 patent drawing
  • US20250156088A1 patent drawing
  • US20250156088A1 patent drawing

AI summary

In some implementations, a memory device may determine, from a list of key-value pair sets, a key-value pair set. The memory device may identify, from the key-value pair set selected from the list of key-value pair sets, a first key that is included in at least one other key-value pair set from the list of key-value pair sets. The memory device may identify, from the key-value pair set selected from the list of key-value pair sets, a second key that is not included in at least one other key-value pair set from the list of key-value pair sets. The memory device may form a new key-value pair set that excludes the first key and includes the second key. The memory device may replace the key-value pair set selected from the list of key-value pair sets with the new key-value pair set.