Semiconductor Memory Device with Known-Data Storage for Accurate Reading
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Solution Overview
Problem
Conventional semiconductor memory devices face issues in accurately reading data from memory cells due to inappropriate reading voltages and comparative currents, leading to incorrect data retrieval.
Innovation Solution
A semiconductor memory device and method that include a memory cell array with a known-data storage area for determining the appropriateness of reading voltages and comparative currents, using a decoder to apply appropriate voltages and a comparison circuit to verify the accuracy of data read, ensuring correct data retrieval by adjusting voltages and currents based on stored determination data.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If conventional reading voltage and comparative current are used, then the memory device operates with simple control, but data reading accuracy deteriorates due to inappropriate voltage/current values
Solution Approach 1:
The patent applies preliminary action by pre-storing determination data in the memory cell array before actual data reading operations. This determination data contains reference information about appropriate reading voltages and comparative currents for different memory cells. When reading data, the control circuit first retrieves and compares this pre-stored determination data to select the optimal reading parameters, thereby ensuring accurate data reading without requiring complex real-time adjustment mechanisms.
Solution Approach 2:
The memory device applies self-service by using its own internal memory cells to store determination data that characterizes the optimal reading conditions for each memory cell. The control circuit automatically retrieves and utilizes this self-stored information to determine appropriate reading voltages and comparative currents, eliminating the need for external calibration equipment or complex control algorithms. The system serves itself by leveraging its own stored data to optimize its reading operations.
2Reliability
If determination data is stored in a separate nonvolatile storage unit, then data loss prevention is improved, but the memory device structure becomes more complex
Solution Approach 1:
The patent applies merging by integrating the determination data storage function directly into the memory cell array itself. Instead of using a separate nonvolatile storage unit, the determination data is stored in specific memory cells within the array. This consolidation eliminates the need for additional dedicated storage hardware, reducing device complexity while maintaining the reliability benefits of nonvolatile storage for critical reading parameters.
Solution Approach 2:
The memory cell array applies universality by serving dual functions: storing both determination data (for optimizing reading operations) and user data (for actual information storage). The same memory cells that hold user information also contain determination data that characterizes optimal reading conditions. This multi-functionality eliminates the need for separate dedicated storage structures, simplifying the overall device architecture while ensuring reliable data loss prevention through nonvolatile storage characteristics.
Data Source
AI summary
A semiconductor memory device and a data reading method capable of appropriately reading data stored in memory cells are provided. The semiconductor memory device includes: a memory cell array including multiple memory cells and having a known-data storage area storing determination data used for determining appropriateness or inappropriateness of a value of each of a reading voltage applied to a memory cell when reading data stored in the memory cell and a comparative current used for a comparison with a current flowing through a memory cell according to stored data; a decoder that applies the reading voltage to a memory cell to be read according to an address representing the memory cell to be read; and a sense amplifier including a comparison circuit that outputs a comparison result acquired by comparing a current flowing through the memory cell to be read 66 according to stored data with the comparative current.