Memory Device Global Local Latch Collision Prevention
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Solution Overview
Problem
In memory devices like SRAM, the transmission of new address and data information from global I/O to local I/Os before a previous write operation is complete can cause collisions, leading to increased device cycle time, which is undesirable.
Innovation Solution
The implementation of local data and address latches controlled independently of the global latching clock signals, allowing for longer data and address information retention and synchronization with local clock and enable signals, thereby preventing collisions during write operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If new address and data information is transmitted from global I/O to local I/Os before a previous write operation is complete, then transmission speed is improved, but collisions occur leading to increased device cycle time
Solution Approach 1:
The patent segments the latch control into two independent parts: global latching clock signals for the global data latch, and local clock signals for the local data latch. This segmentation allows independent control of data retention at different hierarchical levels, enabling the local latch to hold data longer than the global latch without causing collisions, thus resolving the contradiction between transmission speed and device cycle time.
Solution Approach 2:
The patent implements preliminary action by having the local data latch retain address and data information for a longer duration before transmission to the memory cell. This preliminary retention ensures that new information is ready and synchronized before the previous write operation completes, preventing collisions while maintaining efficient operation.
2Reliability
If local latches retain data longer, then collision prevention is improved, but device complexity increases
Solution Approach 1:
The patent divides the latch control system into globally synchronized latches and locally controlled latches with independent clock signals. This segmentation enables differentiated retention periods: global latches use standard clocking while local latches use extended retention clocking, achieving collision prevention without uniformly increasing complexity across the entire system.
Solution Approach 2:
The patent applies local quality by providing different clock signal characteristics to different parts of the system: the global data latch receives globally synchronized clock signals for standard operation, while the local data latch receives local clock signals with extended retention periods. This localized differentiation achieves collision prevention only where needed (at the local latch) without adding unnecessary complexity elsewhere.
Data Source
AI summary
A memory device includes a memory bank with a memory cell connected to a local bit line and a word line. A first local data latch is connected to the local bit line and has an enable terminal configured to receive a first local clock signal. A word line latch is configured to latch a word line select signal, and has an enable terminal configured to receive a second local clock signal. A first global data latch is connected to the first local data latch by a global bit line, and the first global data latch has an enable terminal configured to receive a global clock signal. A global address latch is connected to the word line latch and has an enable terminal configured to receive the global clock signal. A bank select latch is configured to latch a bank select signal, and has an enable terminal configured to receive the second local clock signal.