Memory Device Page Buffer Latch Verify Voltage Optimization
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Solution Overview
Problem
Current memory devices face inefficiencies in programming operations due to the lack of effective methods for managing multiple program states and verify voltages, leading to prolonged programming times and reduced performance.
Innovation Solution
The memory device incorporates a page buffer system with latches that store pre-verify and main verify information, allowing for efficient programming by determining the appropriate voltage levels for bit lines based on the program states, and a control logic that manages these operations to optimize programming speed.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If traditional verify operations are performed for all program states, then programming accuracy is ensured, but programming time increases
Solution Approach 1:
The patent applies preliminary action by performing a pre-verify operation before the main verify operation. The pre-latch stores pre-verify information indicating whether to apply a pre-verify voltage having a lower potential level than the main verify voltage during verify operations. This preliminary verification step allows the system to skip unnecessary main verify operations, thereby reducing programming time while maintaining accuracy for states that require full verification.
Solution Approach 2:
The patent implements skipping by allowing the memory device to bypass certain verify operations based on pre-latch information. When the pre-latch indicates that a pre-verify voltage should be applied, the system can skip the main verify operation for that particular program state, rushing through the verification process selectively to reduce overall programming time while maintaining reliability.
2Productivity
If multiple latches are used to store verify information, then programming efficiency improves, but device complexity increases
Solution Approach 1:
The patent applies segmentation by dividing the verify information storage into two distinct latches: a pre-latch for storing pre-verify information and a main latch for storing main verify information. This segmentation allows each latch to have a specific, simplified function, improving programming efficiency through organized information management while keeping individual latch structures relatively simple.
Solution Approach 2:
The patent implements multi-functionality by having the pre-latch and main latch work together in a unified verify operation system. The pre-latch information guides whether to apply pre-verify voltage, and the main latch stores main verify information, creating a universal verify mechanism that handles multiple program states through a coordinated latch system rather than requiring separate complex structures for each state.
Data Source
AI summary
The present disclosure relates to a memory device may include a plurality of memory cells coupled to a selected word line and to be programmed to one of first to n-th program states distinguished from each other based on threshold voltages thereof, a sensing latch storing data sensed from a bit line coupled to one memory cell, a pre-latch storing pre-verify information and a plurality of data latches storing data to be stored in the one memory cell, wherein at least one data latch stores main verify information on the main verify voltage during verify operations for the first program state to a threshold program state among the first to n-th program states until the verify operation for the threshold program state passes, and wherein the pre-latch stores the main verify information on the n-th program state after the verify operation for the threshold program state passes.