Semiconductor Memory Device Stacked Layer Segmentation
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Solution Overview
Problem
Current semiconductor memory devices face challenges in optimizing the configuration and manufacturing process for high-speed and efficient read operations, particularly in reducing electrostatic capacities and stabilizing transistor operations while maintaining cost-effectiveness.
Innovation Solution
The semiconductor memory device incorporates a configuration with multiple memory layers, a transistor layer, and global bit lines, where transistors are connected to bit line select lines, and semiconductor layers are positioned to enhance channel formation and reduce electrostatic capacity, allowing for selective electrical conduction during read operations. The manufacturing method involves a staircase-shaped structure and alternating layers to optimize transistor and memory cell integration.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If transistors are connected to bit line select lines with multiple memory layers, then read operation speed is improved, but electrostatic capacity increases causing instability
Solution Approach 1:
The bit line select lines are divided into multiple segments corresponding to different memory layers. Each segment is independently controlled by separate transistor gates, allowing selective activation of specific layers during read operations. This segmentation reduces the electrostatic capacity burden on any single transistor while enabling fast access to specific memory layers.
Solution Approach 2:
The patent transitions from a two-dimensional planar structure to a three-dimensional stacked structure with multiple memory layers arranged vertically. This dimensional change allows multiple bit line select lines to be formed in the vertical direction, reducing lateral interference and electrostatic capacity while maintaining high-speed read operations across multiple layers.
2Adaptability or versatility
If multiple memory layers are integrated with transistors, then device functionality is improved, but manufacturing complexity increases
Solution Approach 1:
The manufacturing process merges the formation of transistor gates and bit line select lines into a single integrated structure. The same conductive layers and insulating layers are used to form both transistor components and bit line select line segments, reducing the number of separate manufacturing steps while achieving multiple memory layers with full functionality.
Solution Approach 2:
The conductive layers in the stacked structure serve multiple functions simultaneously: they form transistor gates, bit line select line segments, and electrical interconnects between different memory layers. This multi-functionality reduces manufacturing complexity by eliminating the need for separate dedicated structures for each function.
3Productivity
If semiconductor layers are positioned to enhance channel formation, then transistor performance is improved, but manufacturing precision requirements increase
Solution Approach 1:
The semiconductor layers are positioned with specific local quality variations: they are arranged to form channels only in regions where transistor gates are present, while maintaining insulation in other regions. This localized positioning approach enhances channel formation and transistor performance without requiring extreme precision across the entire device structure.
Solution Approach 2:
Insulating layers are introduced as intermediary structures between the semiconductor layers and other conductive elements. These intermediary insulating layers provide precise spatial definition and electrical isolation, enabling accurate channel formation without requiring direct high-precision positioning of semiconductor layers relative to all other components.
Data Source
AI summary
A semiconductor memory device includes a substrate, memory layers, a first wiring disposed at a position closer to the substrate than memory layers or a position farther from the substrate than memory layers, a transistor layer disposed between memory layers and the first wiring, and a second wiring connected to the memory layers and the transistor layer. Each of memory layers includes a memory unit, a first semiconductor layer connected between the memory unit and the second wiring, a first electrode opposed to the first semiconductor layer, a third wiring connected to the first electrode, a second semiconductor layer electrically connected to one end portion of the third wiring, and a second electrode opposed to the second semiconductor layer. The transistor layer includes a third semiconductor layer connected between the first wiring and the second wiring, and a third electrode opposed to the third semiconductor layer.