Memory Device Line Swap Circuit for Error Cell Redirection
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Solution Overview
Problem
The increasing number of error cells in semiconductor memory devices due to advanced manufacturing processes reduces production yield and memory capacity, necessitating effective detection and repair methods.
Innovation Solution
A memory device and central processing unit incorporating line swap and channel swap circuits that connect internal data lines and channels with external lines based on driving signals, allowing for error detection and swapping to redirect data through redundancy cell arrays for repair.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If advanced manufacturing process technology is used to increase memory capacity, then memory capacity increases, but the number of error cells increases
Solution Approach 1:
The memory device is divided into normal cell arrays and redundancy cell arrays, allowing separation of functional memory storage from error correction resources. This segmentation enables independent management of good and defective cells, maintaining high capacity while dedicating specific resources to error repair.
Solution Approach 2:
The patent changes the operational parameters of data lines by introducing swap circuits that can alter connection configurations. By dynamically changing which external data line connects to which internal data line, the system can redirect data away from error cells and toward functional cells, effectively adapting to manufacturing defects without reducing capacity.
2Productivity
If the number of error cells increases, then production yield decreases, but implementing detection and repair methods can improve yield
Solution Approach 1:
The swap circuit serves multiple functions: it acts as a normal data transmission path during regular operation and simultaneously functions as an error detection and repair mechanism when activated. This multi-functionality allows yield improvement without proportionally increasing device complexity, as the same hardware structure adapts to different operational modes.
Solution Approach 2:
The swap circuit acts as an intermediary between internal memory cells and external data lines, providing a buffer layer that can detect errors and redirect data flow. This intermediary structure enables complex error handling functionality while keeping the core memory array simple and efficient.
3Measurement precision
If line swap circuit swaps external data lines to detect errors, then error detection capability improves, but circuit complexity increases
Solution Approach 1:
The line swap circuit implements dynamic reconfigurability, allowing data line connections to be changed based on operational needs. This dynamic switching capability enables the same physical circuit to perform both normal data transmission and error detection functions, improving measurement precision without permanently increasing structural complexity.
Data Source
AI summary
A memory device includes a first memory cell array connected to a first internal data line; a second memory cell array connected to a second internal data line; and a line swap circuit configured to connect the first and second internal data lines with first and second external data lines based on an externally received driving signal. The line swap circuit is configured such that, when the driving signal has a first logic level, the line swap circuit connects the first and second internal data lines with the first and second external data lines, respectively, and when the driving signal has a second, different logic level, the line swap circuit swaps the first and second external data lines so that the first internal data line is connected to the second external data line and the second internal data line is connected to the first external data line.