Semiconductor Memory Device Local Bit Line Pre-Charging
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Solution Overview
Problem
Existing semiconductor memory devices face challenges in reducing power consumption, particularly due to excessive pre-charging of global bit lines which increases power consumption as the number of memory cells increases, and erroneous data reading from floating global bit lines.
Innovation Solution
The semiconductor memory device incorporates transistors Na and Nb to pre-charge local bit lines independently of global bit lines, using N-channel-type MOS transistors for efficient pre-charging and reducing power consumption by avoiding excessive charging of global bit lines, and utilizing distinct control signals for each column to prevent erroneous data reading.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If global bit lines are pre-charged in conventional semiconductor memory devices, then data reading capability is maintained, but power consumption increases excessively as the number of memory cells increases
Solution Approach 1:
The patent segments the bit line pre-charging function into two independent parts: local bit lines (BL0, BL1) and global bit lines (GBL0, GBL1). Local bit lines are pre-charged through dedicated pre-charge transistors (Na, Nb) while global bit lines remain floating during write operations. This segmentation allows selective pre-charging of only the necessary local bit lines without unnecessarily charging the entire global bit line network, thereby reducing power consumption while maintaining data reading capability.
2Use of energy by moving object
If global bit lines are kept floating to reduce power consumption, then power consumption decreases, but erroneous data reading occurs
Solution Approach 1:
The patent applies preliminary action by pre-charging the local bit lines (BL0, BL1) before memory operations. The pre-charge transistors (Na, Nb) are activated in advance to set known voltage levels on local bit lines, ensuring that even when global bit lines remain floating, the local bit lines have predetermined states that prevent erroneous data reading. This preliminary preparation of local bit line states maintains reading accuracy without requiring global bit line pre-charging.
3Quantity of substance
If the number of memory cells is increased to improve storage capacity, then storage capacity increases, but power consumption increases due to excessive global bit line pre-charging
Solution Approach 1:
The patent divides the bit line hierarchy into local and global segments, allowing storage capacity to be scaled by adding more memory cells connected to shared global bit lines without proportionally increasing pre-charging power consumption. Only the local bit lines directly connected to active memory cells need pre-charging, while global bit lines serving multiple memory cells remain floating. This enables storage capacity expansion with sub-linear power consumption growth.
4Use of energy by moving object
If local bit lines are pre-charged independently using N-channel MOS transistors, then pre-charging efficiency improves and power consumption reduces, but device complexity increases
Solution Approach 1:
The pre-charge transistors (Na, Nb) are designed to serve multiple functions: they pre-charge local bit lines during write operations, maintain local bit line states during read operations, and can be controlled by unified control signals (WBar, RBar) for both write and read cycles. This multi-functionality reduces the need for separate dedicated transistors for each operation type, thereby limiting the increase in device complexity while achieving power consumption reduction through independent local bit line pre-charging.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach reduces power consumption by eliminating the need for excessive global bit line pre-charging and minimizing erroneous data readings, resulting in a more efficient semiconductor memory device.
Implementation Method 1
A first transistor has a current channel connected to a power supply voltage and a first local bit line. A second transistor has a current channel connected to the power supply voltage and a second local bit line.
Data Source
AI summary
A semiconductor memory device includes a memory cell, a pair of local bit lines connected to the memory cell, first and second transistors, one end of the current channel of each connected to a power supply and the other end of the current channel of each connected to one of the local bit lines, third and fourth transistors, one end of the current channel of each connected to one of the local bit lines, the other end of the current channel of each connected to one of the global bit lines, fifth and sixth transistors, one end of the current channel of each connected to one of the global bit lines and the other end of the current channel of which connected to the power supply. The device further includes a control unit configured to control the transistors.