Memory Device Local Data Lines Reduce Power Consumption
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Solution Overview
Problem
In AI and machine learning applications, memory devices face limitations in bandwidth and high power consumption due to data movement through wiring and substrates, leading to performance degradation.
Innovation Solution
The memory device architecture is enhanced by using local data lines instead of main data lines for data access, with logic circuits disposed within subarrays to perform calculations, reducing the need for data line amplifiers and minimizing power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by stationary object
If data is accessed through main data lines (MDQ) in conventional memory devices, then data can be transferred between subarrays, but power consumption increases and bandwidth overhead increases due to the long data line length
Solution Approach 1:
The patent segments the data access paths by introducing local data lines (LDQ) within each subarray and restricting main data lines (MDQ) to connect only adjacent subarrays. This segmentation reduces the effective length of data lines used for most operations, thereby reducing power consumption while maintaining bandwidth through localized data processing via sense amplifiers and logic circuits
Solution Approach 2:
The patent introduces a new dimension of data processing by enabling logic circuits within subarrays to perform calculations on data before it leaves the subarray. This dimensional change in data flow (from purely vertical MDQ access to horizontal LDQ processing within subarrays) reduces the need for long-distance data transmission, lowering power consumption while maintaining or improving effective bandwidth
2Productivity
If data movement between controller and memory device is performed through wiring and substrate, then data can be transferred, but bandwidth is limited by the number of wiring and drawing in substrate
Solution Approach 1:
The patent merges data storage and data processing functions within the same subarray structure by incorporating logic circuits directly into subarrays. This merging eliminates the need for separate data movement paths between controller and memory device for processing operations, thereby increasing effective bandwidth without proportionally increasing wiring complexity
Solution Approach 2:
The patent introduces sense amplifiers and local logic circuits as intermediary elements within subarrays that can process data locally before transmission. These intermediaries reduce the burden on main data lines by performing preliminary processing, effectively increasing bandwidth utilization without requiring proportional increases in substrate wiring
3Ease of operation
If data is accessed through long main data lines (MDQ) in conventional memory devices, then data can be transferred between subarrays, but the overhead in bandwidth increases
Solution Approach 1:
The patent applies local quality by enabling each subarray to perform data processing operations independently through integrated logic circuits. This local capability reduces the need for data to traverse long main data lines for processing, thereby reducing bandwidth overhead while maintaining ease of operation through localized data access and processing
Data Source
AI summary
A memory device is provided. The memory device includes: a plurality of subarrays, a row controller, a column controller, a plurality of sense amplifiers, a plurality of sub word line drivers, and a plurality of logic circuits. Each of the subarrays are electrically coupled to each other. The row controller is configured to control at least a row of the subarrays. The column controller is configured to control at least one column of the subarrays. The sense amplifiers are adapted to each of the subarrays are enabled during a data access operation. The sub word line drivers are disposed adjacent to each of the subarrays and provides a driving signal corresponds to the subarrays. The plurality of logic circuits is disposed in the subarrays and configured to perform the data access operation.