Memory Device Local Target Data Search
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Conventional memory devices require significant time to locate and compare target data across multiple memory banks, leading to inefficiencies in data processing due to the need for external processors to receive and compare data one bank at a time, which slows down operation speed.
Innovation Solution
Incorporating a memory device with multiple memory banks, each equipped with a latch circuit and comparison circuit connected to a data transmission path, allowing for simultaneous comparison of stored data with target data received from an external processor, thereby reducing comparison time and improving operation speed.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If data comparison is performed externally one bank at a time, then device complexity is reduced, but operation speed deteriorates
Solution Approach 1:
The patent merges the comparison circuit functionality into the memory device itself, combining storage and comparison functions in a single integrated system. This allows multiple memory banks to perform comparisons simultaneously within the memory device, eliminating the need for external sequential processing and significantly improving operation speed.
Solution Approach 2:
The patent transitions from sequential one-dimensional processing (one bank at a time) to parallel multi-dimensional processing by enabling simultaneous comparison operations across multiple memory banks. This dimensional change in processing architecture allows all memory banks to operate concurrently, dramatically increasing throughput and speed.
2Productivity
If multiple memory banks are equipped with latch and comparison circuits, then data processing efficiency is improved, but device complexity increases
Solution Approach 1:
The latch circuits and comparison circuits are designed as universal components that can handle various data types and comparison operations. Each memory bank is equipped with these multi-functional circuits that can perform both data storage and comparison tasks, enabling parallel processing across all banks while maintaining design consistency and reducing overall system complexity.
Solution Approach 2:
The memory device performs comparison operations autonomously using its own internal latch and comparison circuits, without requiring external processor intervention for each comparison. This self-service capability allows the memory device to independently execute comparison tasks, improving productivity while the standardized circuit design prevents excessive complexity increase.
3Loss of time
If target data is stored in latch circuits within each memory bank, then comparison time is reduced, but manufacturing complexity increases
Solution Approach 1:
The latch circuits store target data in advance within each memory bank before the actual comparison operation begins. This preliminary action of pre-positioning data in the latch circuits eliminates data transfer delays during comparison, significantly reducing comparison time. The standardized latch circuit design maintains manufacturing ease despite the added functionality.
Data Source
AI summary
A memory device can include a plurality of memory banks coupled to an input/output bus and a memory controller coupled to the plurality of memory banks. The memory controller can be configured to control operations of the plurality of memory banks, where each of the plurality of memory banks can include a bank array including a plurality of memory cells configured to store data, a latch circuit coupled to the input/output bus, where the latch circuit can be configured to store target data received via the input/output bus to provide stored target data, and a comparison circuit coupled to the latch circuit, where the comparison circuit can be configured to compare stored data output by the bank array with the stored target data to provide result data to the memory controller.