Semiconductor Memory Device Logic Code Equalizes Sensing Operations
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
As memory devices approach their physical scaling limits, existing semiconductor memory devices face challenges in improving read performance after programming data, particularly in efficiently managing threshold voltage states and minimizing sensing operations across multiple logical pages.
Innovation Solution
The semiconductor memory device employs a logic code to equalize the number of sensing operations required to read data across logical pages, utilizing weak read levels and assigning specific read levels to minimize errors and optimize read performance, while also using a 3D or 2D memory cell array structure with multi-level cells to store data.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If multiple logical pages are stored in a single physical page using multi-level cells, then storage density is improved, but the number of sensing operations required to read data increases
Solution Approach 1:
The patent divides the reading process into multiple sensing operations, each targeting specific threshold voltage ranges. By segmenting the read operation into distinct sensing steps (first sensing operation for first threshold voltage range, second sensing operation for second threshold voltage range), the system can efficiently read data from multiple logical pages stored in a physical page without excessive complexity.
Solution Approach 2:
The patent applies different read levels selectively based on the logical page being read. When reading data from a specific logical page, the system uses a read level optimized for that page's data characteristics. This local optimization ensures that each sensing operation uses the appropriate read level for the specific threshold voltage range, improving overall read efficiency.
2Measurement precision
If different read levels are used for different logical pages, then reading accuracy is improved, but the complexity of managing multiple read levels increases
Solution Approach 1:
The patent implements a dynamic read level selection mechanism where the read level is adjusted based on the current logical page being accessed. The control logic dynamically determines which read level to use by examining the logical page identifier, allowing the system to adapt the sensing operation parameters in real-time without requiring complex hardware modifications.
Solution Approach 2:
The system changes the read level parameter based on the logical page number. By mapping logical pages to specific read levels (e.g., first read level for first logical page, second read level for second logical page), the patent optimizes reading accuracy for each page while managing complexity through systematic parameter assignment rather than requiring complex adaptive algorithms.
3Reliability
If weak read levels are assigned to specific logical pages, then sensing errors are minimized, but the programming operation complexity increases
Solution Approach 1:
The patent performs preliminary actions during the programming operation by pre-determining which logical pages will use weak read levels. The control logic identifies logical pages that require weak read levels before the actual reading occurs, allowing the system to prepare appropriate read level assignments in advance. This prevents sensing errors by ensuring the correct read levels are used from the start.
Solution Approach 2:
The system uses feedback information from the programming operation to determine read level assignments. By monitoring the programming results and identifying which logical pages have data characteristics that benefit from weak read levels, the system can adaptively assign read levels in subsequent reading operations. This feedback mechanism improves reliability while managing complexity through intelligent decision-making.
Data Source
AI summary
A semiconductor memory device, and a method of operating the same, includes a memory cell array and a peripheral circuit. The memory cell array includes memory cells, each storing N bits of data. The peripheral circuit performs a program operation on a physical page including selected memory cells. The peripheral circuit is configured to receive pieces of data of N logical pages and program the pieces of data of the N logical pages to the physical page based on a logic code. The logic code is determined to equalize numbers of sensing operations required to read the pieces of data of the N logical pages. Weak read levels are assigned, using the logic code, to read data of a logical page for which the number of sensing operations is smallest.