Memory Device Asynchronous Mode Register Update Notification

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Solution Overview

Problem

Memory devices face bandwidth consumption issues due to frequent polling of operating parameters by hosts to determine mode adjustments, which can lead to congestion on the command/address and data buses, especially when the mode register contents have not changed.

Innovation Solution

A memory device generates a notification to the host when information in the mode register is updated, allowing the host to poll only when necessary, thereby reducing bandwidth consumption on both buses.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If the host frequently polls the memory device to check for mode register updates, then the host can detect changes promptly, but the command/address bus and data bus experience increased bandwidth consumption and congestion

Engineering Contradiction:
Improvetimely detection of mode register updatesVSAvoidbandwidth consumption on command/address bus and data bus
Core Design Contradiction:
ReliabilityVSLoss of energy

Solution Approach 1:

The memory device implements a feedback mechanism by actively notifying the host when mode register contents change. The notification circuit generates an update notification that is communicated to the host, eliminating the need for continuous polling. This feedback approach ensures timely detection of changes while significantly reducing bus bandwidth consumption compared to frequent polling.

Inventive Principle:
Principle #23Feedback

Solution Approach 2:

The memory device performs self-service by autonomously detecting when its mode register contents have changed and initiating the notification process without requiring external polling from the host. The device monitors its own state and independently generates update notifications, reducing the communication overhead on the buses.

Inventive Principle:
Principle #25Self-service

2Loss of energy

If the host polls the memory device less frequently to reduce bandwidth consumption, then bus congestion is reduced, but the detection of mode register updates is delayed

Engineering Contradiction:
Improvebandwidth consumption on command/address bus and data busVSAvoiddetection delay of mode register updates
Core Design Contradiction:
Loss of energyVSLoss of time

Solution Approach 1:

The feedback mechanism ensures that the host is notified immediately when mode register updates occur, eliminating detection delays associated with infrequent polling. The notification circuit provides real-time information about changes, allowing the host to respond promptly without consuming excessive bus bandwidth.

Inventive Principle:
Principle #23Feedback

Solution Approach 2:

The notification circuit acts as an intermediary that bridges the memory device and host, providing a dedicated communication path for update notifications. This intermediary mechanism allows change information to be transmitted efficiently without burdening the command/address bus and data bus, thus reducing bandwidth consumption while maintaining timely detection.

Inventive Principle:
Principle #24Intermediary (Mediator)

3Reliability

If the memory device continuously monitors and notifies the host of all potential changes, then update detection is maximized, but the device complexity increases

Engineering Contradiction:
Improvecompleteness of update detectionVSAvoidcomplexity of notification circuit and monitoring mechanism
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The memory device leverages its existing self-monitoring capabilities for mode register management and extends this self-service function to detect changes. By reusing existing internal logic that already tracks mode register state, the notification circuit achieves comprehensive update detection without proportionally increasing complexity.

Inventive Principle:
Principle #25Self-service

Solution Approach 2:

The notification circuit is designed to work with the memory device's existing mode register management infrastructure, allowing a single monitoring mechanism to serve multiple functions: tracking mode register changes, generating notifications, and interfacing with the host. This multi-functionality approach maximizes update detection capability while minimizing additional complexity.

Inventive Principle:
Principle #6Universality (Multi-functionality)

Data Source

PatentUS20240289060A1Methods for asynchronously signaling updated information from a memory device to a host and memory devices and systems employing the same
Publication Date: 2024.08.29 LODESTAR LICENSING GROUP LLC
  • US20240289060A1 patent drawing
  • US20240289060A1 patent drawing
  • US20240289060A1 patent drawing

AI summary

Memory devices, memory systems, and methods of operating memory devices and systems are disclosed in which a memory device can asynchronously indicate to a connected host that information in a mode register has been changed, obviating the need for repeated polling of the information and thereby reducing both command/address bus and data bus bandwidth consumption. In one embodiment, a memory device comprises a memory; a mode register storing information corresponding to the memory; and circuitry configured to, in response to the information in the mode register being modified by the memory device, generate a notification to a connected host device.