Memory Device Multi-Cell Error Correction Method
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Solution Overview
Problem
Memory devices with integrated non-volatile memories of different types face challenges in data reliability due to varying data retention and cycling endurance in ECC message bits and parity bits, requiring an effective error correction method.
Innovation Solution
A memory device and method that utilize a plurality of memory cells, including a first type and a second type of physical cells, where a memory control circuit writes data into the first type cell and verifies its accuracy; if the data is not correct, it rewrites it into the second type cell, enhancing error correction and data reliability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If data is written only into the first type physical cell, then the cycling rate is improved, but the data reliability deteriorates due to varying data retention and cycling endurance
Solution Approach 1:
The memory system is segmented into two types of physical cells with different characteristics. The first type physical cell is used for normal data storage to maintain high cycling rate, while the second type physical cell is used for error correction to ensure data reliability. This segmentation allows each cell type to be optimized for its specific function.
Solution Approach 2:
The patent changes the physical parameters of different cell types to suit different functions. The first type physical cell has parameters optimized for fast writing and high cycling endurance, while the second type physical cell has parameters optimized for data retention and error correction capability. This parameter differentiation resolves the contradiction between cycling rate and data reliability.
2Reliability
If different types of physical cells are used for message bits and parity bits, then the data retention and cycling endurance are optimized, but the device complexity increases
Solution Approach 1:
The memory control circuit is designed with multi-functionality to handle both types of physical cells. It can perform normal write operations to the first type cell and error correction operations to the second type cell using the same control logic. This universality reduces the need for separate dedicated circuits for each cell type, thereby limiting the increase in device complexity.
Solution Approach 2:
The system implements self-service error correction where the memory control circuit automatically detects errors in the first type physical cell and corrects them by writing corrected data to the second type physical cell without requiring external intervention. This self-service mechanism simplifies the overall system architecture while maintaining high reliability.
3Manufacturing precision
If verification is performed on every write operation to the first type physical cell, then the data accuracy is improved, but the loss of time increases
Solution Approach 1:
Instead of verifying every single write operation, the system performs verification selectively based on error detection needs. The memory control circuit verifies data accuracy primarily when error correction is required, rather than on every write operation. This partial verification approach maintains data accuracy while significantly reducing the time loss associated with continuous verification.
Solution Approach 2:
The system uses the second type physical cell as a disposable error correction resource. When verification fails or errors are detected in the first type cell, the corrected data is written to the second type cell which has higher data retention but is not used for normal operations. This approach trades the limited capacity of the second cell type for time efficiency, avoiding continuous verification of every write operation.
Data Source
AI summary
A memory device and a multiple cells error correction in a memory cell is provided. The memory device includes a plurality of memory cells and a memory control circuit. Each of the memory cells includes a first type physical cell and a second type physical cell. The memory control circuit is coupled to each of the memory cells. The memory control circuit writes a writing data into the first type physical cell and verifies the data stored in the first type physical cell is same as the writing data or not. The writing data is set and processed by performing a write operation. The memory control circuit writes the writing data into the second type physical cell when the data stored in the first type physical cell is not same as the writing data.