Memory Device Multi-Plane Controller Architecture
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Solution Overview
Problem
Current memory systems face challenges in simultaneously performing read, program, and erase operations on multiple planes of a memory device without interrupting ongoing operations, leading to inefficiencies in data storage and retrieval processes.
Innovation Solution
A memory device architecture that includes individual and common operation controllers, along with a peripheral circuit for generating operation voltages, allows for independent and simultaneous execution of read, program, and erase operations across multiple planes, enabling concurrent data access and management.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If a single operation controller is used to manage read, program, and erase operations on multiple planes, then the device complexity is reduced, but the productivity and operational efficiency deteriorate due to inability to perform simultaneous operations
Solution Approach 1:
The operation controller is segmented into multiple independent controllers, each dedicated to specific operations (read, program, erase) on specific planes. This segmentation enables parallel operation control across multiple planes simultaneously, resolving the contradiction between simplified structure and operational efficiency.
Solution Approach 2:
Each operation controller is designed with multi-functional capability to handle different operation types (read, program, erase) on different planes. This universality allows the system to maintain reduced complexity while achieving high productivity through parallel operations.
2Device complexity
If operations are performed sequentially on multiple planes, then the device complexity remains low, but the loss of time increases due to interrupted operations
Solution Approach 1:
Multiple operation controllers enable continuous useful action by allowing read, program, and erase operations to proceed simultaneously on different planes without interruption. Each controller independently manages its assigned operations, eliminating idle time and maintaining continuous productive action across the memory system.
Solution Approach 2:
Operation controllers are pre-configured with specific operation types and plane assignments, enabling them to immediately execute operations without waiting for sequential scheduling. This preliminary preparation of control structures eliminates operation delays and time loss.
3Productivity
If multiple operation controllers are implemented to enable simultaneous operations on multiple planes, then the productivity is improved, but the device complexity increases
Solution Approach 1:
The controller architecture is segmented into specialized units, each handling specific operation types on specific planes. This segmentation improves productivity through parallel processing while managing complexity by creating modular, independent control units with well-defined interfaces.
Solution Approach 2:
The system transitions from a single-dimension sequential control model to a multi-dimensional parallel control architecture. By adding the dimension of concurrent operation control across multiple planes, the system achieves high productivity while the modular structure manages the increased complexity through systematic organization.
Data Source
AI summary
The present technology relates to a memory device. A memory device according to the present technology may include a plurality of planes, individual operation controllers configured to respectively control read operations on the plurality of planes, a common operation controller configured to control a program operation or an erase operation on any one of the plurality of planes, a command decoder configured to provide a read command among the plurality of commands to an individual operation controller that controls a plane that is indicated by an address that corresponds to the read command among the individual operation controllers, and configured to provide a program command or an erase command among the plurality of commands to the common operation controller, and a peripheral circuit configured to generate operation voltages that are used for the read operations, the program operation, and the erase operation.