Memory Device Erasing via Negative Fixed Oxide Charge
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
The development of semiconductor memory devices faces a trade-off between increasing programming and erasing speeds and maintaining information retention characteristics, as a thin tunneling oxide layer enhances speed but compromises retention, while a thick blocking oxide layer improves retention but hampers control over the channel region.
Innovation Solution
A method involving the sequential formation of a tunneling oxide layer, a charge storing layer, and a blocking oxide layer on a semiconductor substrate, followed by annealing under specific gas atmospheres (e.g., O2, RuO, NH3) at temperatures of 650° C. or more to impart a negative fixed oxide charge to the blocking oxide layer, improving erasing characteristics.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If a thin tunneling oxide layer is used, then programming and erasing speed is improved, but information retention characteristics deteriorate
Solution Approach 1:
The patent introduces a new parameter - negative fixed oxide charge in the blocking oxide layer - to resolve the trade-off between speed and retention. By controlling the fixed oxide charge density (Qf) to be negative (e.g., -5×10^11 to -5×10^12 q/cm²), the patent enables thin tunneling oxide layers (improving speed) while maintaining retention characteristics through the compensating effect of negative charges that prevent electron leakage.
2Reliability
If a thick blocking oxide layer is used, then information retention characteristics are improved, but control over the channel region deteriorates
Solution Approach 1:
The patent changes the electrical parameter of the blocking oxide layer by introducing negative fixed oxide charge. This allows the blocking oxide layer to be thinner (improving control) while still maintaining retention characteristics through the negative charge that compensates for electron leakage, thus resolving the contradiction between thickness and control.
3Ease of manufacture
If the blocking oxide layer has positive fixed oxide charge, then manufacturing is simplified, but erasing characteristics deteriorate
Solution Approach 1:
The patent changes the sign of the fixed oxide charge parameter from positive to negative. This parameter change fundamentally improves erasing speed by preventing back-tunneling of electrons from the charge trapping layer to the gate electrode, while the negative charge can be introduced through standard annealing processes in oxygen or nitrogen atmospheres, maintaining ease of manufacture.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances the erasing speed and retention characteristics of memory devices by increasing the band gap energy of the blocking oxide layer, preventing back tunneling and maintaining electrical stability over numerous programming/erasing cycles.
Implementation Method 1
the blocking oxide layer 14 on the charge storing layer 13 blocks electrons from leaking into the gate electrode layer 14 while the electrons are trapped in the trap site of the charge storing layer 13
Implementation Method 2
annealing the semiconductor substrate including the tunneling oxide layer, the charge storing layer, and the blocking oxide layer under a gas atmosphere so that the blocking oxide layer has a negative fixed oxide charge
Data Source
AI summary
In a method of manufacturing a memory device having improved erasing characteristics, the method includes sequentially forming a tunneling oxide layer, a charge storing layer, and a blocking oxide layer on a semiconductor substrate; annealing the semiconductor substrate including the tunneling oxide layer, the charge storing layer, and the blocking oxide layer under a gas atmosphere so that the blocking oxide layer has a negative fixed oxide charge; forming a gate electrode on the blocking oxide layer with the negative fixed oxide charge and etching the tunneling oxide layer, the charge storing layer, and the blocking oxide layer to form a gate structure; and forming a first doped region and a second doped region in the semiconductor substrate at sides of the gate structure by doping the semiconductor substrate with a dopant.