Memory Device Noise Cancellation for Stable Page Buffer Sensing
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Solution Overview
Problem
Noise in the source and ground voltages affects the smooth operation of semiconductor devices and integrated circuits, particularly memory devices, leading to inefficiencies in memory operations.
Innovation Solution
A memory device equipped with a noise cancellation circuit that generates a second ground voltage to offset noise by determining a reference voltage based on a first ground voltage, thereby reducing and canceling noise in the system.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a noise cancellation circuit is added to the memory device, then the reliability of memory operations is improved by reducing noise voltage, but the device complexity increases
Solution Approach 1:
A noise cancellation circuit is introduced as an intermediary component between the power supply and the memory device. This circuit includes a noise cancellation unit that generates a noise voltage signal based on detected noise in the power supply, and an addition unit that adds this noise signal to the power supply voltage to cancel out the original noise, thereby improving reliability without requiring fundamental redesign of the memory architecture
Solution Approach 2:
The noise cancellation circuit implements feedback by continuously detecting the noise voltage in the power supply through a detection unit, using this information to generate a corresponding noise cancellation signal through a noise cancellation unit, and adjusting the output voltage accordingly. This closed-loop feedback mechanism enables dynamic noise compensation while maintaining stable operation
2Ease of operation
If the ground voltage is stabilized through noise cancellation, then the smooth operation of memory devices is improved, but the ease of manufacture decreases due to additional circuit requirements
Solution Approach 1:
The noise cancellation functionality is segmented into distinct modular units: a detection unit that monitors noise voltage, a noise cancellation unit that generates compensation signals, and an addition unit that combines the signals. This segmentation allows each module to be designed and manufactured independently, simplifying the overall manufacturing process while achieving stable ground voltage operation
Data Source
AI summary
The present disclosure provides for memory apparatuses and systems including noise cancellation circuits, and operating methods thereof. In some embodiments, a memory device includes a first pad, a memory cell plane comprising a plurality of memory cells, a page buffer circuit, and a noise cancellation circuit. The page buffer circuit is configured to sense the memory cell plane, and identify, based on the sensing of the memory cell plane, a state stored in a memory cell of the plurality of memory cells, according to a ground voltage. The noise cancellation circuit is configured to receive a first ground voltage from the first pad, determine a reference voltage based on the first ground voltage, generate a second ground voltage that offsets a noise voltage, based on the reference voltage, and output the second ground voltage to the page buffer circuit.