Memory Device NTT Operator with Butterfly Unit and Buffers
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Solution Overview
Problem
Existing memory devices face challenges in efficiently performing Number-Theoretic Transform (NTT) operations, particularly due to high power consumption in GPU-based methods and limitations in processing high-precision operations with FPGA-based methods.
Innovation Solution
A memory device with an integrated operator and multiple buffers is proposed, where the operator performs butterfly operations using a butterfly unit, and the buffers store data for each stage of the operation, enabling efficient in-place updates and pipelining for improved processing speed.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If GPU-based acceleration method is used for NTT operation, then processing speed is improved, but power consumption increases significantly
Solution Approach 1:
The patent segments the NTT operation into multiple stages and uses multiple buffers to store data for each stage. This segmentation allows the operator to process data in smaller chunks across different time steps, reducing the computational burden on any single unit and thereby lowering overall power consumption while maintaining processing speed through pipelined execution.
Solution Approach 2:
The patent performs preliminary actions by pre-storing data in multiple buffers before the actual computation begins. This allows the operator to retrieve data directly from buffers during computation rather than continuously accessing external memory, reducing memory access overhead and power consumption while maintaining high processing speed.
2Use of energy by moving object
If FPGA-based acceleration method is used for NTT operation, then power consumption is reduced, but processing capability for high-precision operations is limited
Solution Approach 1:
The patent creates a universal operator that can handle both high-precision operations and efficient processing. The operator is designed to work with multiple buffers and support arbitrary polynomial lengths and modulo values, making it versatile enough to handle high-precision requirements while maintaining the low power consumption characteristics of the memory device architecture.
Solution Approach 2:
The patent changes the operational parameters by supporting arbitrary polynomial lengths and modulo values through the operator. This flexibility allows the system to adapt to different precision requirements and cryptographic applications, enabling high-precision operations to be performed efficiently with reduced power consumption compared to fixed-function FPGA implementations.
3Use of energy by moving object
If FPGA-based acceleration method is used for NTT operation, then power consumption is reduced, but processing speed is limited by maximum length constraints
Solution Approach 1:
The patent introduces dynamic elements through pipelining and the use of multiple buffers that can be selectively accessed during different time steps. This dynamic approach allows the operator to process data of arbitrary length efficiently, overcoming the fixed maximum length constraints of traditional FPGA methods while maintaining low power consumption through optimized data flow management.
Solution Approach 2:
The patent ensures continuity of useful action through pipelined processing where data is continuously fed through the operator from buffers. This continuous operation eliminates idle time and maximizes processing throughput for arbitrary polynomial lengths, achieving high productivity while maintaining the low power consumption benefits of the memory device architecture.
4Speed
If multiple buffers are used for each stage of operation, then processing speed is improved through pipelining, but hardware area increases
Solution Approach 1:
The patent merges the buffer storage function with the memory device structure itself, utilizing existing memory resources to store data for different operation stages. This merging approach reduces the need for separate dedicated buffers, thereby minimizing additional hardware area overhead while still enabling pipelined processing and high processing speed through efficient data management.
Data Source
AI summary
A memory device includes a memory cell array, an operator comprising a logic circuit configured to perform an operation comprising a plurality of stages, and a plurality of buffers configured to store first data and second data corresponding to a plurality of operation commands received from a host for each of the plurality of stages, respectively, wherein the operator comprises a butterfly unit configured to perform butterfly operations based on at least one of the first data and the second data.