Memory Device ODT Control via Mode Registers
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Solution Overview
Problem
The removal of ODT pins in new memory technologies such as DDR5, LPDDR5, and HBM2 leads to increased turn-around time latency in memory devices, necessitating internal logic to adjust resistance and timing settings for improved signal integrity during read and write operations.
Innovation Solution
Incorporating control logic within memory devices to program mode registers with 3-bit values for resistance and timing settings, allowing for adjustments to ODT-related parameters like RTT and tODTLon/off to optimize signal integrity, using coding schemes and timing diagrams to manage resistance and timing values across data buses.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If ODT pins are removed in new memory technologies, then device complexity is reduced, but turn-around time latency increases
Solution Approach 1:
The patent removes ODT pins from the physical interface and extracts the ODT control functionality into internal mode registers within the memory device. This eliminates the need for external ODT pin connections while preserving the essential termination control capabilities through register-based configuration of RTT values and tODTLon/off timing parameters.
Solution Approach 2:
The patent introduces mode registers as an intermediary mechanism between the host controller and the ODT control logic. These registers serve as the mediation interface, allowing the host to program resistance and timing settings without requiring direct physical ODT pins, thus reducing interface complexity while maintaining functional control.
2Ease of manufacture
If ODT pins are removed, then ease of manufacture is improved, but signal integrity deteriorates
Solution Approach 1:
By extracting ODT control to internal registers, the patent simplifies the physical interface structure, reducing the number of pins and associated routing complexity in the memory device package. This extraction improves ease of manufacture while the internal control logic preserves signal integrity through programmed termination.
Solution Approach 2:
The patent enables dynamic adjustment of termination parameters (RTT resistance values and tODTLon/off timing) through mode register programming. This parameter flexibility allows optimization of signal integrity for different operating conditions and memory configurations, compensating for the removal of dedicated ODT pins.
3Loss of time
If internal control logic is added to program mode registers, then turn-around time latency is reduced, but device complexity increases
Solution Approach 1:
The patent implements multi-functional mode registers that handle multiple ODT control functions (resistance setting, timing control, termination enable/disable) within a single register structure. This universal approach consolidates what would otherwise require multiple separate control mechanisms, reducing overall device complexity while enabling precise latency optimization.
Solution Approach 2:
The patent enables pre-programming of ODT parameters in mode registers before memory operations commence. By establishing termination settings in advance through register configuration, the system eliminates runtime negotiation delays that would otherwise increase turn-around time, while the control logic remains relatively simple.
Data Source
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AI summary
Examples include techniques for command based on die termination (ODT). In some examples, values are programmed to registers at a memory device to establish one or more internal resistance termination (RTT) settings of ODT at the memory device. Values are also programmed to registers at the memory device to establish one more settings for timing of ODT latency. Programmed values may be changed in order to adjust a signal integrity for the memory device during read or write operations.