Memory Device Output Unit Combining Product and Variable Information

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Solution Overview

Problem

Current non-volatile memory devices face limitations in quickly outputting read information due to complex operations and timing constraints, which affect their efficiency and reliability.

Innovation Solution

A memory device architecture that includes an enable signal generation unit, a storage unit for product information, and an output unit that combines product and variable information using a single internal clock, allowing for rapid and synchronized output of read information.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Speed

If complex operations and timing constraints are used in conventional memory devices, then data storage reliability is maintained, but read information output speed is limited

Engineering Contradiction:
Improveread information output speedVSAvoidoperation complexity
Core Design Contradiction:
SpeedVSDevice complexity

Solution Approach 1:

The read information is segmented into two distinct components: fixed product information (stored in storage unit 310) and variable information (generated by information generation unit 320). This segmentation allows each component to be processed and output independently through separate pathways, eliminating the need for complex timing coordination between different information types and enabling faster overall output.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

Product information is pre-stored in the storage unit 310 during manufacturing or initialization, and the information generation unit 320 is pre-configured with generation logic. When a read command is received, these pre-prepared components can be quickly combined and output without requiring complex real-time processing, thus improving output speed while reducing operational complexity.

Inventive Principle:
Principle #10Preliminary action

2Speed

If multiple clocks are used for outputting fixed and variable information, then timing flexibility is provided, but speed restrictions and timing constraints are imposed

Engineering Contradiction:
Improveinformation output speedVSAvoidtiming constraint
Core Design Contradiction:
SpeedVSLoss of time

Solution Approach 1:

The patent merges the output operations of fixed product information and variable information into a single unified output stream controlled by one clock signal. The control logic 300 combines both information types and outputs them simultaneously through the same data output interface, eliminating the need for multiple clock signals and their associated timing constraints, thereby enabling faster and more flexible output.

Inventive Principle:
Principle #5Merging (Combining)

3Productivity

If separate output operations are used for product information and variable information, then information integrity is maintained, but output efficiency is reduced

Engineering Contradiction:
Improveoutput efficiencyVSAvoidinformation integrity
Core Design Contradiction:
ProductivityVSReliability

Solution Approach 1:

The data output interface is designed with universal functionality to handle both fixed product information and variable information through the same pathway. The control logic 300 manages the combination and routing of both information types, allowing the single output interface to efficiently process diverse information types without compromising integrity, thus improving overall output efficiency.

Inventive Principle:
Principle #6Universality (Multi-functionality)

Data Source

PatentUS10452277B2Memory device and operating method thereof
Publication Date: 2019.10.22 SK HYNIX INC
  • US10452277B2 patent drawing
  • US10452277B2 patent drawing
  • US10452277B2 patent drawing

AI summary

The present disclosure relates to a memory device and an operating method thereof. A memory device includes an enable signal generation unit generating an enable signal in response to a command; a storage unit storing product information of the memory device; an information generation unit generating variable information of the memory device; and an output unit combining the product information from the storage unit with the variable information from the information generation unit and outputting the combined information in response to the enable signal.