Memory Device with Oxide Semiconductor Buffer Layers
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Solution Overview
Problem
Existing semiconductor memory devices face challenges in achieving high reliability, large storage capacity, small area footprint, and low manufacturing costs due to trap centers at the interface between semiconductor and insulator, which affect the threshold voltage and reliability of the memory device.
Innovation Solution
A semiconductor device is designed with a specific structure on the side surface of a conductor, comprising multiple layers of insulators and semiconductors, including oxide semiconductors, to enhance electrical connections and reduce trap centers, thereby improving reliability and storage capacity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If a plurality of memory elements are stacked and connected in series to form a three-dimensional memory cell array, then storage capacity per unit area is increased, but trap centers are formed at the interface between semiconductor and insulator, which adversely influences reliability
Solution Approach 1:
An oxide semiconductor layer is introduced as an intermediary between the insulator and the semiconductor to prevent direct contact. This intermediate layer acts as a buffer that eliminates trap centers at the interface, thereby maintaining reliability while preserving the stacked memory structure for high storage capacity
Solution Approach 2:
The patent employs a composite structure combining oxide semiconductor with conventional semiconductor materials. This composite approach leverages the advantages of oxide semiconductors (low defect density, stable electrical characteristics) to mitigate the harmful effects of interface trap centers while maintaining the benefits of three-dimensional stacking for increased storage capacity
2Area of stationary object
If memory cells are stacked vertically to increase storage capacity, then area footprint is reduced, but manufacturing complexity increases
Solution Approach 1:
The patent transitions from planar two-dimensional memory architecture to three-dimensional vertical stacking. By utilizing the vertical dimension, storage capacity is dramatically increased while the area footprint is minimized, achieving high-density memory in a compact form factor
3Ease of manufacture
If conventional semiconductor-insulator interfaces are used in stacked memory, then manufacturing process is simpler, but threshold voltage shifts occur due to trap centers
Solution Approach 1:
The patent changes the material parameter by using oxide semiconductor instead of conventional semiconductor materials at the critical interface region. This material substitution fundamentally alters the interface properties, eliminating trap centers and enabling precise threshold voltage control while maintaining manufacturing feasibility
Data Source
AI summary
A highly reliable memory device is provided. On a side surface of a first conductor extending in a first direction, a first insulator, a first semiconductor, a second insulator, a second semiconductor, and a third insulator are provided in this order when seen from the first conductor side. A first region overlapping with a second conductor with the first insulator, the first semiconductor, the second insulator, the second semiconductor, and the third insulator therebetween, and a second region overlapping with a third conductor with the first insulator, the first semiconductor, the second insulator, the second semiconductor, and the third insulator therebetween are provided in the first conductor. In the second region, a fourth conductor is provided between the first insulator and the first semiconductor.