Semiconductor Memory Device Pad Alignment
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Solution Overview
Problem
Current semiconductor memory devices have a large size due to the separate fabrication of memory cell arrays and logic circuits on different chips, leading to increased manufacturing complexity and costs.
Innovation Solution
A semiconductor memory device structure where first and second pads on the memory and circuit chips, respectively, are aligned with pass transistors at the same pitch, allowing for bonding and reducing the size by shortening wiring lengths and simplifying the manufacturing process.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If memory cell array and logic circuit are fabricated on separate chips, then manufacturing flexibility is improved, but device size increases
Solution Approach 1:
The circuit chip is stacked on top of the memory chip in a three-dimensional configuration, with the memory cell array on the first substrate and the logic circuit on the second substrate. This vertical nesting arrangement allows both chips to occupy overlapping footprint areas, reducing the overall device footprint while maintaining separate fabrication processes for each chip type.
Solution Approach 2:
The invention transitions from a planar two-dimensional layout to a three-dimensional stacked configuration. By utilizing the vertical dimension (stacking the circuit chip on the memory chip), the device achieves compact integration without compromising the manufacturing flexibility of separate chip fabrication.
2Adaptability or versatility
If separate chips are used for memory and logic, then manufacturing complexity increases, but design flexibility is improved
Solution Approach 1:
The device is divided into two separately fabricated chips: a memory chip containing the memory cell array and a circuit chip containing the logic circuit. This segmentation allows each chip to be optimized and manufactured independently using appropriate processes, then integrated through bonding, thereby maintaining design flexibility while managing manufacturing complexity through modular assembly.
Solution Approach 2:
A bonding interface with aligned pads serves as an intermediary between the memory chip and circuit chip. This bonding structure facilitates the connection of row lines from the memory cell array to pass transistors in the logic circuit, enabling separate fabrication while achieving functional integration.
3Length of moving object
If pads are aligned with pass transistors at the same pitch, then wiring length is reduced, but alignment precision requirements increase
Solution Approach 1:
The bonding pad structure employs asymmetric design where the second pads on the circuit chip are specifically aligned with the pitch of pass transistors, while the first pads on the memory chip are aligned with the pitch of row lines. This asymmetric pitch alignment optimizes wiring length for each chip type while maintaining overall alignment through the bonding interface.
Solution Approach 2:
The invention changes the pitch parameter of the second pads to match the pitch of pass transistors, rather than using a uniform pitch for all pads. This parameter optimization reduces wiring length and improves signal integrity, while the bonding process compensates for the increased alignment precision requirements through precise pad-to-pad registration.
Data Source
AI summary
A semiconductor memory device includes a plurality of first pads disposed in one surface of a memory chip which includes a memory cell array and a plurality of row lines coupled to the memory cell array, and coupled to the row lines, respectively; and a plurality of second pads disposed in one surface of a circuit chip which is boned to the one surface of the memory chip, coupled to pass transistors, respectively, of the circuit chip, and bonded to the first pads, respectively. The second pads are aligned with the pass transistors, with the same pitch as a pitch of the pass transistors.